1. Future Hardware Development for discussion with JLU Giessen
Zhen’An LIU
Inst. High Energy Physics, Beijing
DAQ session, PANDA General Meeting, GSI
DEC

2. Zhen'An LIU, IHEP/Beijing
Outlook
Current Status/short Review
New development Idea
Discussion + near Plan
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

3. Zhen'An LIU, IHEP/Beijing
Outlook
Current Status/short Review
New development Idea
Discussion + near Plan
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

4. Current Status/Review
BESIII Trigger
Pipelined processing
Pipeline clock 41.65MHz
Latency: 6.4us
Fast transmission
RocketIO
1.67Gbps
Fiber isolation w/ FEE
Hardware + HLF
Detector
switch
Level 1
FEE
pipeline
Readout
buffer
Farms
Disk
Time Reference
0 s
6.4s
Ev.Filter
PowerPC
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

5. System Block diagram of BESIII Trigger
Near Detectors
Counting Room
Fast Control
FC Daughters
High Lights: Optical Isolation-no ground loop current
TOF FEE
Global Trigger Logic
TOFPR
Hit/Seg Count
Track Match
MDC FEE
MFT
Track Seg. Finder
Track Finder
EMC FEE
Energy Balance
TCBA
TC Sum
Etotal Energy
L1P
Cluster Counting
MU FEE
FastOR
Mu track
BEPCII RF
TTC
499.8 MHz
41.65 MHz
6.4 s
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

6. Zhen'An LIU, IHEP/Beijing
Fiber connection
Fast Control
TDC
MDC
Trigger
EMC/TOF/GTL
Trigger
MDC
Optical Fibers
TOF
Optical
Cables
EMC
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

7. Zhen'An LIU, IHEP/Beijing
BESIII DAQ structure
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

8. Review and Collaboration
BESIII TDAQ
1 level Hardware + HLF
1.67Gbps only for trigger
VME based FEE, bandwidth <500Mbps
Independent branches, no interconnection/feature extraction
Commercial PPC boards
Collaboration on BESIII Upgrade + PANDA
TrigLab/IHEP + II Phys. Inst/JLU Giessen
New TDAQ structure for BESIII, PANDA, and others
Gigabit fiber transmission
Data preprocessing w/ fast FPGA
interconnection/feature extraction
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

9. Key device: High Performance Compute Node (HPCN)
New structure and key device:
Dedicated processors with very large I/O bandwidth based on FPGAs to have what ever logic we need (HPCN)
HPCN Resources
4 FPGAs + local dram
High speed I/O capabilities
4 x Gbit Ethernet
4 x Optical links
2 Embedded PPC on each FPGA
Can run a normal Linux
Large number of logic cells
ATCA crate architecture
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

10. HPCN block and features
High Performance Compute Power:
5x (Virtex-4 FPGA + 2Gb DDR2)
~32Gbps Bandwidth
13x RocketIO to backplane
5x Gigabit Ethernet
8x Optical Link
2 Embedded PowerPC in each FPGA
Real time Linux
ATCA compliant
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

11. Zhen'An LIU, IHEP/Beijing
First Prototype
FPGA #1-4
FPGA #O
Optical
Backplane
Ethernet
DDR2 sockets
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

12. Zhen'An LIU, IHEP/Beijing
2nd version prototype
SFP pluggable
Mono RJ45 socket
Higher bandwidth
Front Pannel
Better LEDs
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

13. Zhen'An LIU, IHEP/Beijing
Future Development
New version for PANDA
No urgent need
Possible
Faster FPGA, Virtex V
Cheaper FPGA,Spartan 6
Belle II PXD:
Onboard Memmory
20GB
DDR3?
XTCA for Physics at IHEP
Carrier Board
AMC card
RTM
Trigger and Timing
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

14. Zhen'An LIU, IHEP/Beijing
XTCA program at IHEP
AMC IO board
Standard AMC board
Stacked connector
Demonstration prototypes under developing at IHEP
Stacked connectors
Operational in full system
Committee will develop specs
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

15. Zhen'An LIU, IHEP/Beijing
XTCA program at IHEP
Mechanical design complete
Drawing mods underway
Specs draft started
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing

16. Discussion and Outlook
Short of manpower also at IHEP
Better joint development for PANDA/PXD/XTCAforPhysics
Baselines:
DDR3
Carrier + AMC
Single layered AMC?
Gigabit IO via AMC panel, not RTM
June 2010:
Draft circuits for AMC and Carrier
Order parts
End 2010
New version I hope
Thanks!
Dec PANDA GM,GSI
Zhen'An LIU, IHEP/Beijing