1. Embedded System Design Center
ARM Processor
ARM7TDMI Microprocessor
Branching and Exception Handling
M.S. Ramaiah School of Advanced Studies

2. Objectives To understand different operating modes of ARM Processor.
To understand how exceptions are handled in ARM Processor and how to return from exception
To know exception priority and vector addresses.
To learn direct manipulation of status registers.
To understand branch instruction, subroutine handling and changing between ARM and THUMB mode with branching.
To learn how high-level constructs like if, switch and for statements can be implemented in ARM assembly code.

3. ARM Exceptions
Exceptions are used to handle unexpected events which may arise due to
Externally generated interrupts
An attempt by the processor to execute an undefined instruction
Accessing privileged operating system functions
ARM Exceptions Classification
Exception generated as direct effect of instruction execution
SWI, Undefined, prefetch aborts
Exception generated as a side-effect of an instruction
Data aborts
Exception generated externally, unrelated to program execution
Reset, IRQ and FIQ

4. Embedded System Design Center
ARM Processor
Processor Modes
The ARM has six operating modes:
User (unprivileged mode under which most tasks run)
Fast interrupt request Mode-FIQ (entered when a high priority (fast) interrupt is raised)
Interrupt Mode-IRQ (entered when a low priority (normal) interrupt is raised)
Supervisor Mode-SVC (entered on reset and when a Software Interrupt instruction is executed)
Abort Mode- ABT (used to handle memory access violations)
Undefined Mode-UND (used to handle undefined instructions)
M.S. Ramaiah School of Advanced Studies

5. Processor Modes
All modes except User mode are referred to as privileged modes. They have full access to system resources and can change mode freely.
Modes other than User mode are entered to service exceptions, or to access privileged resources. Five of them are known as Exception modes:
IRQ, FIQ, Supervisor, Abort, Undefined Modes
Applications that require task protection usually execute in User mode.
Some embedded applications might run entirely in Supervisor or System modes. It is intended for use by Operating system with the Exception Mode.

6. Use of modes and registers by exceptions
Typically,an application runs in user mode,but servicing exception requires privileged(i.e., non-user mode) operation.
An exception changes the processor mode and this in turn means that each exception handler has access to a certain subset of the banked registers:
Its own r13 or stack pointer(sp_mode)
Its own r14 or Link Register(lr_mode)
Its own Saved Program Status Register(spsr_mode).
In case of a FIQ,each exception handler has to five more general purpose registers(r8_FIQ to r12_FIQ).

7. Exception Priorities Vector address Exception Type Exception mode
Priority
(1=high,6=low)
0x0
Reset
Supervisor(SVC) 1
0x4
Undefined Instruction
Undef 6
0x8
Software Interrupt(SWI)
0xC
Prefetch Abort
Abort 5
0x10
Data Abort 2
0x14
Reserved
Not applicable
0x18
Interrupt(IRQ) 4
0x1C
Fast Interrupt(FIQ) 3

8. Operating modes CPSR[4:0] Mode Use Registers 10000 User
Normal user code
user
10001
FIQ
Processing faster interrupts
_fiq
10010
IRQ
Processing standard interrupts
_irq
10011
SVC
Processing software interrupts
_svc
10111
Abort
Processing memory faults
_abt
11011
Undef
Handling undefined instructions
_und
11111
System
Running privileged operating system tasks

9. The Current Program Status Register(CPSR)
The CPSR holds:
copies of the Arithmetic Logic Unit (ALU) status flags
the current processor mode
interrupt disable flags.
The ALU status flags in the CPSR are used to determine whether conditional instructions are executed or not.
On Thumb-capable processors, the CPSR also holds the current processor state (ARM or Thumb).

10. Saved Program Status Registers (SPSRs)
The SPSRs are used to store the CPSR when an exception is taken.One SPSR is accessible in each of the exception-handling modes.
User mode and System mode do not have an SPSR because they are not exception handling modes.

11. ARM Register Organisation
Embedded System Design Center
ARM Processor
ARM Register Organisation
ARM General registers and Program Counter
ARM Program Status Registers
r15 (pc)
r14 (lr)
r13 (sp)
r14_svc
r13_svc
r14_irq
r13_irq
r14_abt
r13_abt
r14_undef
r13_undef
User32 / System
FIQ32
Supervisor32
Abort32
IRQ32
Undefined32
cpsr
sprsr_fiq
spsr_abt
spsr_svc
spsr_fiq
spsr_irq
r12
r10
r11 r9 r8 r7 r4 r5 r2 r1 r0 r3 r6
r14_fiq
r13_fiq
r12_fiq
r10_fiq
r11_fiq
r9_fiq
r8_fiq
spsr_undef
* Shaded indicates Banked Registers
M.S. Ramaiah School of Advanced Studies

12. THUMB Register Organisation
Thumb General registers and Program Counter
Thumb Program Status Registers
User / System
FIQ
Supervisor
Abort
IRQ
Undefined
CPSR
sprsr_fiq
SPSR_ABT
SPSR_SVC
SPSR_FIQ
SPSR_IRQ
SPSR _UND PC LR SP r7 r4 r5 r2 r1 r0 r3 r6
PC_ FIQ
LR_ FIQ
SP_FIQ
PC_ SVC
LR_ SVC
SP_SVC
PC_ ABT
LR_ ABT
SP_ABT
PC_ IRQ
LR_ IRQ
SP_IRQ
PC_ UND
LR_ UND
SP_UND

13. Handling the Exception
ARM coded
veneers
Thumb coded
application
Save CPU &
Register state
Switch to
ARM state
Switch to
Thumb state
Entry Veneer
Handle the
exception
Restore CPU
& register state
Switch to Thumb
State and return
Switch to
ARM state
Exit veneer

14. Processor response to an Exception
Embedded System Design Center
ARM Processor
Processor response to an Exception
When an exception occurs, the core:
Copies CPSR into SPSR_<mode>
Sets appropriate CPSR bits
If core implements ARM Architecture 4T and is currently in Thumb state, then
ARM state is entered.
Mode field bits are changed to indicate new mode.
Disables IRQ and in case of FIQ disables further fast interrupts.
Maps in appropriate banked registers
Stores the “return address” in LR_<mode>
Sets PC to vector address
Exceptions, in order serviced, are:
Reset - supervisor mode
Data abort - abort mode
External Fast Interrupt Request - FIQ mode (eg DMA)
External Interrupt Request - IRQ mode
Instruction Prefetch abort - abort mode
Software Interrupt (SWI)- supervisor mode (typically used to extend operating system)
Undefined instruction - undefined mode
Only one memory location for each vector
Each vector contains branch to that particular exception handler
FIQ vector is last one. This allows its handler to be run sequentially from that address, removing need for branch and its associated delays. Important because speed is essential for FIQ.
Interrupt routine’s responsibility to clear interrupt condition.
Can return using one instruction
See exception handling module for details.
M.S. Ramaiah School of Advanced Studies

15. Returning from an Exception Handler
Embedded System Design Center
ARM Processor
Returning from an Exception Handler
To return, exception handler needs to:
Restore CPSR from SPSR_<mode>
Restore PC from LR_<mode>
Above two operations cannot be carried out simultaneously.
If CPSR is restored first – mode gets changed – r14 is no longer accessible.
If PC is restored first – exception handler looses control and cannot do restoration of CPSR.
Exceptions, in order serviced, are:
Reset - supervisor mode
Data abort - abort mode
External Fast Interrupt Request - FIQ mode (eg DMA)
External Interrupt Request - IRQ mode
Instruction Prefetch abort - abort mode
Software Interrupt (SWI)- supervisor mode (typically used to extend operating system)
Undefined instruction - undefined mode
Only one memory location for each vector
Each vector contains branch to that particular exception handler
FIQ vector is last one. This allows its handler to be run sequentially from that address, removing need for branch and its associated delays. Important because speed is essential for FIQ.
Interrupt routine’s responsibility to clear interrupt condition.
Can return using one instruction
See exception handling module for details.
M.S. Ramaiah School of Advanced Studies

16. With return address in R14
To return from a SWI or undefined instruction trap use:
MOVS PC, R14
To return from an IRQ, FIQ or prefetch abort use:
SUBS PC, R14, #4
To return from a data abort to retry the data access use:
SUBS PC, R14, #8

17. Adjustment to return address
IRQ and FIQ must return one instruction early in order to execute the instruction that was “usurped” for the exception entry.
Prefetch abort must return one instruction early to execute the instruction that had caused a memory fault when first requested.
Data abort must return two instructions early to retry the data transfer instruction, which was the instruction before the one usurped for exception entry.

18. Return address in Stack
Embedded System Design Center
ARM Processor
Return address in Stack
Handler can save all registers along with return address on to stack
STMFD sp!,{r0-r12, lr} ; stack all registers
; and the return address
In that case the restoration of user registers and PC can be implemented with a single multiple register transfer instruction such as:
LDMFD sp!,{r0-r12, pc}^ ; load all the registers
; and return automatically
However in order to adjust the return mechanism r14 must be adjusted before being saved onto the stack.
M.S. Ramaiah School of Advanced Studies

19. FIQ MODE ABORT MODE supports data transfer or channel process.
externally generated by taking the nFIQ input LOW.
FIQ may be disabled by setting the CPSR’s F flag
ABORT MODE
indicates that the current memory access cannot be completed.
There are two types of abort:
Prefetch abort -occurs during an instruction prefetch.
Data abort -occurs during a data access.
The exception will not be taken until the instruction reaches the head of the pipeline.

20. Supervisor Mode Undefined Mode
The Supervisor Mode is entered in following situations.
Power on Reset
On reset
When SWI (Software Interrupt) instruction is executed
Undefined Mode
used to extend either the THUMB or ARM instruction set by software emulation.
After emulating the failed instruction, the trap handler-
restores the CPSR and returns to the instruction following the undefined instruction.

21. The Program Status Registers (CPSR and SPSRs)
Embedded System Design Center
ARM Processor
The Program Status Registers (CPSR and SPSRs)
Copies of the ALU status flags (latched if the
instruction has the "S" bit set).
Mode N Z C V 28 31 8 4
I F T
Condition bits
Condition Code Flags
N = Negative result from ALU flag.
Z = Zero result from ALU flag.
C = ALU operation Carried out
V = ALU operation oVerflowed
Mode Bits
M[4:0] define the processor mode.
Interrupt Disable bits.
I = 1, disables the IRQ.
F = 1, disables the FIQ.
T Bit (Architecture v4T only)
T = 0, Processor in ARM state
T = 1, Processor in Thumb state
Current Program Status Register (CPSR) can be considered as an extension of the PC. It contains the:
condition code flags, N,Z,C,V.
interrupt (FIQ, IRQ) disable bits
mode bits
T bit
Software must never change value in TBIT. If this happens, the processor will enter an unpredictable state.
Lower 28 bits known as the "control bits".
Bits other than the specified interrupt and mode bits are reserved for future processors, and no program should depend on their values.
The condition codes in the CPSR will be preserved or updated depending on the value of the S bit in the instruction.
Some instructions do alter condition flags regardless of “S”, ie CMN, CMP, TST and TEQ (return no other result).
Mode field bigger than needs to be - just history.
Only six modes valid on pre-ARM Architecture v4 chips.
SPSRs
Also five other PSRs, the Saved Program Status Registers, one for each privilege mode, into which a copy of the CPSR is loaded when an exception occurs.
M.S. Ramaiah School of Advanced Studies

22. Embedded System Design Center
ARM Processor
Condition Flags
Flag
Logical Instruction
Arithmetic Instruction
Negative (N=‘1’)
No meaning
Bit 31 of the result has been set. Indicates a negative number in signed operations
Zero (Z=‘1’)
Result is all zeroes
Result of operation was zero
Carry (C=‘1’)
After Shift operation ‘1’ was left in carry flag
Result was greater than 32 bits
oVerflow (V=‘1’)
Result was greater than 31 bits Indicates a possible corruption of the sign bit in signed numbers
N flag SUB r0, r1, r2 where r1<r2
Z flag SUB r0, r1, r2 where r1=r2 (also used for results of logical operations)
C flag ADD r0, r1, r2 where r1+r2>0xFFFFFFFF
V flag ADD r0, r1, r2 where r1+r2>0x7FFFFFFF
(if numbers are signed, ALU sign bit will be corrupted)
(0x7FFFFFF+0x =0x )
(answer okay for unsigned but wrong for signed)
M.S. Ramaiah School of Advanced Studies

23. PSR Transfer Instructions
Embedded System Design Center
ARM Processor
PSR Transfer Instructions
MRS and MSR allow contents of CPSR/SPSR to be transferred from appropriate status register to a general purpose register.
All of status register, or just the flags, can be transferred.
Syntax:
MRS{<cond>} Rd,<psr> ; Rd = <psr>
MSR{<cond>} <psr>,Rm ; <psr> = Rm
MSR{<cond>} <psrf>,Rm ; <psrf> = Rm
where
<psr> = CPSR, CPSR_all, SPSR or SPSR_all
<psrf> = CPSR_flg or SPSR_flg
Also an immediate form
MSR{<cond>} <psrf>,#Immediate
This immediate must be a 32-bit immediate, of which the 4 most significant bits are written to the flag bits.
Remember using:
MRS -> MR := S ie Make Register equal to Status
MSR -> MS := R ie Make Status equal to Register
M.S. Ramaiah School of Advanced Studies

24. Embedded System Design Center
ARM Processor
Using MRS and MSR
Currently reserved bits, may be used in future, therefore:
they must be preserved when altering PSR
the value they return must not be relied upon when testing other bits.
Thus read-modify-write strategy must be followed when modifying any PSR:
Transfer PSR to register using MRS
Modify relevant bits
Transfer updated value back to PSR using MSR
Note:
In User Mode, all bits can be read but only the flag bits can be written to.
Mode N Z C V 28 31 8 4
I F T
M.S. Ramaiah School of Advanced Studies

25. PSR Bit Sections Format:
N Z C V I F T mode
flags field (f) status field (s) extension field (e) control field(c)
Format:
MSR {<cond>} CPSR_f |SPSR_f, Rm|immediate _f
could be f, s, e, c which apply field mask
Note: status field and extension fields are unused on current ARMs.

26. Conditional Execution
Embedded System Design Center
ARM Processor
Conditional Execution
Most instruction sets only allow branches to be executed conditionally.
However by reusing the condition evaluation hardware, ARM effectively increases number of instructions.
All instructions contain a condition field which determines whether the CPU will execute them.
Non-executed instructions soak up 1 cycle.
Still have to complete cycle so as to allow fetching and decoding of following instructions.
This removes the need for many branches, which stall the pipeline (3 cycles to refill).
Allows very dense in-line code, without branches.
The Time penalty of not executing several conditional instructions is frequently less than overhead of the branch or subroutine call that would otherwise be needed.
M.S. Ramaiah School of Advanced Studies

27. Embedded System Design Center
ARM Processor
The Condition Field 28 31 24 20 16 12 8 4
Cond
1001 = LS - C clear or Z (set unsigned lower or same)
1010 = GE - N set and V set, or N clear and V clear (>or =)
1011 = LT - N set and V clear, or N clear and V set (>)
1100 = GT - Z clear, and either N set and V set, or N clear and V set (>)
1101 = LE - Z set, or N set and V clear,or N clear and V set (<, or =)
1110 = AL - always
1111 = NV - reserved.
0000 = EQ - Z set (equal)
0001 = NE - Z clear (not equal)
0010 = HS / CS - C set (unsigned higher or same)
0011 = LO / CC - C clear (unsigned lower)
0100 = MI -N set (negative)
0101 = PL - N clear (positive or zero)
0110 = VS - V set (overflow)
0111 = VC - V clear (no overflow)
1000 = HI - C set and Z clear (unsigned higher)
4 bit Condition Field refers to the values of the appropriate bits in the CPSR, as indicated on slide.
Most instructions assembled with default condition code "always" (1110, AL).
This means the instruction will be executed irrespective of the flags in CPSR.
The "never" code (1111, NV) is reserved.
This family of conditions will be redefined for future use in other ARM devices.
Use MOV r0, r0 as NOP operation.
Conditional instructions aids code density
remove need for many branches (discussed earlier)
M.S. Ramaiah School of Advanced Studies

28. Embedded System Design Center
ARM Processor
Branch instructions
Branch : B{<cond>} label
Branch with Link : BL{<cond>} sub_routine_label
The offset for branch instructions is calculated by the assembler:
By taking the difference between the branch instruction and the target address minus 8 (to allow for the pipeline).
This gives a 26 bit offset which is right shifted 2 bits (as the bottom two bits are always zero as instructions are word – aligned) and stored into the instruction encoding.
This gives a range of ± 32 Mbytes. 28 31 24
Cond L Offset
Condition field
Link bit 0 = Branch
1 = Branch with link 23 25 27
Branch instructions are PC-relative rather than absolute:
Branch instructions’ encoding contain a signed 2's complement 24 bit offset which is calculated by the assembler from the destination label given in the source code.
M.S. Ramaiah School of Advanced Studies

29. Embedded System Design Center
ARM Processor
Branch instructions
When executing the instruction, the processor:
shifts the offset left two bits, sign extends it to 32 bits, and adds it to PC.
Execution then continues from the new PC, once the pipeline has been refilled.
The "Branch with link" instruction implements a subroutine call by writing PC-4 into the LR of the current bank.
i.e. the address of the next instruction following the branch with link (allowing for the pipeline).
To return from subroutine, simply need to restore the PC from the LR:
MOV pc, lr
Again, pipeline has to refill before execution continues.
The "Branch" instruction does not affect LR.
Note: Architecture 4T offers a further ARM branch instruction, BX
Branch offset must take account of the PC's prefetch offset, which is handled by the assembler
In effect subtracts 8 before using it : PC normally +8 of what actually executing - pipeline.
The Branch with Link (BL) writes the old PC into the link register (R14) of the current bank.
Again PC value saved adjusted for the prefetch offset to point to the next instruction after the BL instruction.
ie saves PC - 4
CPSR has NOT been saved with the PC.
Return using
MOV pc, lr
Branch Instruction takes 3 cycles because of refilling the pipeline. Similarly on return.
M.S. Ramaiah School of Advanced Studies

30. BX Instruction BX : Branch and Exchange
Instruction branches to an address held in register Rm with an optional switch to Thumb execution.
Branch target address is the value of register Rm, with bit[0] forced to zero
Mode of branch target is chosen by setting the CPSR T bit to bit[0] of ARM.
Syntax: BX { <cond>} <Rm>

31. BX Instruction SBO : Should be 0 (Zero) Only
Cond SBO SBO SBO Rm
SBO : Should be 0 (Zero) Only
Rm : Register [31 : 1] which will be transferred to PC. It is essential that the address should be word aligned.

32. Example: if statement C:
if (a < b) { x = 5; y = c + d; } else x = c - d;
Assembler:
; compute and test condition
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
ADR r4,b ; get address for b
LDR r1,[r4] ; get value for b
CMP r0,r1 ; compare a < b
BGE fblock ; if a >= b, branch to false block

33. If statement, cont’d. ; true block MOV r0,#5 ; generate value for x
ADR r4,x ; get address for x
STR r0,[r4] ; store x
ADR r4,c ; get address for c
LDR r0,[r4] ; get value of c
ADR r4,d ; get address for d
LDR r1,[r4] ; get value of d
ADD r0,r0,r1; compute y
ADR r4,y ; get address for y
STR r0,[r4] ; store y
B after ; branch around false block

34. If statement, cont’d. ; false block
fblock ADR r4,c ; get address for c
LDR r0,[r4] ; get value of c
ADR r4,d ; get address for d
LDR r1,[r4] ; get value for d
SUB r0,r0,r1 ; compute a-b
ADR r4,x ; get address for x
STR r0,[r4] ; store value of x
after ...

35. Example: Conditional instruction implementation
; true block
MOVLT r0,#5 ; generate value for x
ADRLT r4,x ; get address for x
STRLT r0,[r4] ; store x
ADRLT r4,c ; get address for c
LDRLT r0,[r4] ; get value of c
ADRLT r4,d ; get address for d
LDRLT r1,[r4] ; get value of d
ADDLT r0,r0,r1 ; compute y
ADRLT r4,y ; get address for y
STRLT r0,[r4] ; store y

36. Conditional instruction implementation, cont’d.
; false block
ADRGE r4,c ; get address for c
LDRGE r0,[r4] ; get value of c
ADRGE r4,d ; get address for d
LDRGE r1,[r4] ; get value for d
SUBGE r0,r0,r1 ; compute a-b
ADRGE r4,x ; get address for x
STRGE r0,[r4] ; store value of x

37. Example: switch statement
switch (test) { case 0: … break; case 1: … }
Assembler:
ADR r2,test ; get address for test
LDR r0,[r2] ; load value for test
ADR r1,switch tab ; load address for switch table
LDR r1,[r1,r0,LSL #2] ; index switch table
switch tab DCD case0
DCD case1
...

38. Embedded System Design Center
ARM Processor
Subroutine calling
AREA Example, CODE, READONLY ; name this blk of code
ENTRY ; mark I instruction to execute
start
MOV r0, #15 ; Set up parameters
MOV r1, #20
BL firstfunc ; Call subroutine
SWI 0x11 ; terminate
firstfunc ; Subroutine firstfunc
ADD r0, r0, r1 ; r0 = r0 + r1
MOV pc, lr ; Return from subroutine ; with result in r0
END ; mark end of file
M.S. Ramaiah School of Advanced Studies

39. Switch statement with subroutines
Embedded System Design Center
ARM Processor
Switch statement with subroutines
AREA ArithGate, CODE ; name this block of code
ENTRY ; mark the first instruction to call
main
MOV r0, #2 ; set up three parameters
MOV r1, #5
MOV r2, #15
BL arithfunc ; call the function
SWI 0x11 ; terminate
arithfunc ; label the function
CMP r0, #4 ; Treat code as unsigned integer
BHI ReturnA1 ; If code > 4 then return first argument
ADR r3, JumpTable ; Load address of the jump table
LDR pc,[r3,r0,LSL #2] ; Jump to appropriate routine
JumpTable
DCD ReturnA1
DCD ReturnA2
DCD DoAdd
DCD DoSub
DCD DoRsb
M.S. Ramaiah School of Advanced Studies

40. Continued….. ReturnA1 MOV r0, r1 ; Operation 0, >4 MOV pc,lr
DoAdd
ADD r0, r1, r2 ; Operation 2
DoSub
SUB r0, r1, r2 ; Operation 3
DoRsb
RSB r0, r1, r2 ; Operation 4
END ; mark the end of this file

41. Summary 7 operating modes: User, FIQ, IRQ, SVC, ABT, UND, SYS
Mode indications in CPSR/SPSR: CPSR[4:0]
Exception handling in ARM Processor: LR, Stack, Vector addresses, Priority
Working with CPSR/SPSR: MSR, MRS
16 Conditional execution on all instructions
Branch Instruction: B, BL
Branch with mode change: BX
Implementation of high level constructs

42. Thank You, Any Questions ?