1. Recent R&D Milestones at GRAPES-3
Atul Jain
On behalf of GRAPES-3 collaboration
9th Workshop on Astroparticle Physics
Cosmic Ray Laboratory, TIFR, Ooty
20 December 2014

2. Hardware R&D
Programmable Logic unit, Fast Counter and Data Acquisition Module
USB Interface module for Sc_Main DAQ
USB Interface module for Sc_Rate DAQ
60 Ch Pulse Width Analyser
Muon Life Time measurement
High Voltage Monitoring DAQ
Amplifier and Discriminator for PRC’s

3. Software R&D GRAPES-3 REMOTE_MON GRAPES-3 WEB_MON
GRAPES-3 Sc_Data Base
GRAPES-3 PRC Fabrication_Data Base
GRAPES-3 on line Shower Display

4. FPGA based 8 Ch. Scalar (2010-2011)
Input Translator
FPGA
USB Interface PC
SALIENT FEATURES
USB Interface
Low Power Consumption
Programmable features
On board Real Time Clock
Team
Prof . S. D. Kale (VIIT)
Rohit (VIIT)
Jatin (VIIT)
Atul Jain (CRL)
R. Sureshkumar ( CRL)

5. Implementation Development boards for Atmel FPGA
PCB for Input Level Translator and microcontroller mounting.
GUI for Windows

6. Real World Test

7. 12th JULY 2011

9. FPGA based 32 Ch. Scalar (2011-2012)
Input Translator
FPGA
USB Interface PC
SALIENT FEATURES
USB Interface
Low Power Consumption
Programable features
On Board Real Time Clock
Interface with Linux OS
Team
Prof . S. D. Kale (VIIT)
Bhaskar Taneja (VIIT)
Abhisekh Gupta (VIIT)
Suraj Kole (VIIT)
Atul Jain (CRL)
K.Manjunath (CRL)
R. Sureshkumar ( CRL)

11. Programmable Logic unit, Fast Scalar & Data Acquisition Module
Most of the experiment requires a
Logic Unit
Fast Scalar
Data Acquisition Module
Conventional Approach
Detector
Amplifier
Discriminator
Logic Unit
Scalar

12. New Approach Salient Features 8 External Inputs
Detector
Integrated
Amp + Disc
Logic Unit
Scalar
DAQ
Computer
Salient Features
8 External Inputs
27 Programmable Logic Combinations
24 Bit Scalar for each Input and Logic Combination
Inbuilt Real Time Clock
Online Graphical Display of Data
Online Data Storage
•Binary file with every sec data for selected channels.
•Text file with Average value for user defined duration
•Text file with Integral Total counts for user defined duration
Suraj Kole, K.Manjunath

15. Serin Varghese

17. Earlier Sc_Main DAQ START / GATE Level-0 Trigger Amplifier &
GRAPES
Amplifier
&
Discriminator
GRAPES
Pulse
Fan-out
GRAPES HV
Dist.
GRAPES
EAS Trigger
GRAPES
Level-1
Trigger
GRAPES
ARRAY
OF DETECTORS
Clear
400…
EAS Trigger
GRAPES
Master
Controller
GRAPES
Real
Time
Clock
ADC
CAEN
GRAPES
TDC
GRAPES
CAMAC
Controller
GRAPES
Memory
Buffer
PCI
CARD
Clear
GPS
Receiver
Meinberg
GATE
START
WINDOWS 98/ ME
WAPP-2008

18. USB Interface module for Sc_Main DAQ
PC’s with PCI interface are outdated
Old Windows Operating system updates are not available
PCI interface card has no support for LINUX OS
Use of old PC’s >>>>>>>>> PC Hanginng
Prone to virus attacks resulting in corrupted events
Pic microcontroller 1Mbytes/sec
FTDI Chip 8Mbytes/sec

19. Present Sc_Main DAQ START / GATE Level-0 Trigger Amplifier &
GRAPES
Amplifier
&
Discriminator
GRAPES
Pulse
Fan-out
GRAPES HV
Dist.
GRAPES
EAS Trigger
GRAPES
Level-1
Trigger
GRAPES
ARRAY
OF DETECTORS
Clear
400…
EAS Trigger
GRAPES
Master
Controller
GRAPES
Real
Time
Clock
ADC
CAEN
GRAPES
TDC
GRAPES
CAMAC
Controller
GRAPES
USB
Interface
Clear
GPS
Receiver
Meinberg
GATE
START
LINUX CENT-OS
WAPP-2008

21. FORMAT ERROR EVENTS ON 13-05-2014
Errors
PCI
USB
Event header
corruption 6
More
Data 23 2
Less 3
TOTAL 31 5
B Hariharan

22. DATA MISMATCH EVENTS COMPARISON BASED ON TRIGGER
PCI
USB
TRIGGER
ACTUAL
EVENTS
MISMATCH %
1FFF
36588
577
1.6
2FFF
32713
1.3
4FFF
73159
231
0.3
8FFF
362260
1431
0.4
TOTAL
34952
1.1
TRIGGER
ACTUAL
EVENTS
MISMATCH %
1FFF
36597
2FFF
4FFF
73168
8FFF
362278
TOTAL
B Hariharan

23. Proposed Sc_Main DAQ START / GATE Level-0 Trigger Amplifier &
GRAPES
Amplifier
&
Discriminator
GRAPES
Pulse
Fan-out
GRAPES HV
Dist.
GRAPES
GRAPES
Level-1
Trigger
GRAPES
Clear
ARRAY
OF DETECTORS
400…
EAS Trigger
ADC
CAEN
GRAPES
TDC
GRAPES
CAMAC
Controller
GRAPES
Master
Controller
RTC
USB
Interface
GPS
Receiver
Meinberg
Clear
GATE
START
LINUX CENT-OS
WAPP-2008

24. USB Interface module for Sc_Rate DAQ
Serin Varghese
Suraj Kole
K.Manjunath

25. 60 Ch Pulse Width Analyser
Salient Features on Board
Pulse Width Analyser
On board Histogram Generation
On board Real Time Clock
Logical O-ring for all 60 Channels
Rate Monitoring for all 60 Channnels
Suraj Kole, K.Manjunath

27. High Voltage Monitoring (2012-2013)
High Voltage Bias of PMT
Linearly stepped down voltage
ADC
USB Interface PC
Team
Prof . V M Aranake (VIIT)
Serin Varghese(VIIT)
Sarrah Lokhandwala (VIIT)
Ashutosh Khedkar (VIIT)
Prof. S.R. Dugad (CRL, TIFR)
Raghunandan (CRL,TIFR)
K. Manjunath ( CRL)

28. Present Status
Prof. S.R. Dugad, Serin Varghere, Sarrah Lokhandwala, K Manjunath

29. High Voltage Monitoring
Salient Features
Monitoring of Voltages upto 3000V with a resolution 0.1V
48 channel monitoring/board - Modular Design
Use of I2C protocol (400KHz to interconnect modules (Use of USB-I2C library - Sarrah Lokhandwala)
Interconnection by I2C Hub – circumventing the inherent shortcomings of the protocol
Individually isolated grounds for protection
Additional protection circuitry.

32. Measurement of Muon Life Time
P Rakshe

33. Software R&D GRAPES-3 REMOTE_MON GRAPES-3 WEB_MON
GRAPES-3 Sc_Data Base
GRAPES-3 PRC Fabrication_Data Base
GRAPES-3 on line Shower Display

34. Thanks