1. The Analysis of Cyclic Circuits with Boolean Satisfiability
Authors: John Backes, Brian Fett, and Marc Riedel
ICCAD ’08
Slide & Present: Chih-Fan Lai
Ref: Slide of Timing Analysis of Cyclic Combinational Circuits

2. Outline Introduction Algorithm Proof of Correctness Discussion
Future Work

3. Introduction Combinational Circuits
Output depend on only current input values
Must have cyclic topologies?

4. Combinational Circuits
The current outputs depend only on the current inputs.
inputs
outputs
combinational
logic
Realm of digital design is mature:
Combinational Circuit:
Circuit does not have any memory, or any internal state.
Performs a mapping from boolean inputs, to boolean outputs.

5. Combinational Circuits
Generally acyclic (i.e., feed-forward) structures. x y z c s
AND OR
XOR

6. Cyclic Combinational Circuits
AND OR
Circuit is cyclic yet combinational x a b 1 x c d

7. Introduction Analyzing Cyclic Circuits Ascertain by controlling value
Shares many properties with logic verification
SAT-based techniques is more efficient
How to analysis
Find feedback arc set
Add dummy variables
Encode entire circuit in terms of ternary-value
Form SAT question

8. Introduction Prior and Related Work CYCLIFY
A methodology for synthesize cyclic circuits
Build within Berkeley SIS environment
Reduce 30% of the area and 25% of the delay
Analysis based on BDD

9. Introduction Circuit Model in this Paper Floating-mode Ternary values
{0, 1, }

10. Circuit Model
Perform static analysis in the “floating-mode”. At the outset:
all wires are assumed to have unknown/undefined values ( ).
the primary inputs assume definite values in {0, 1}.
a “controlling” input
full set of “non-controlling” inputs
unknown/undefined output

11. Circuit Model
Perform static analysis in the “floating-mode”. At the outset:
all wires are assumed to have unknown/undefined values ( ).
the primary inputs assume definite values in {0, 1}. 1 ^ OR
AND
During the analysis, only signals driven (directly or indirectly) by the primary inputs are assigned definite values.

12. Validity of a Cyclic Circuit
Fixed point
A state where no further updates of controlling values are possible
Invalid
For some PI assignment, there are values in the fixed point
Valid
For every PI assignment, there are no values in the fixed point

13. Objective Convert into an acyclic SAT circuit whose
output is 0 ↔ the cyclic circuit is valid

14. Algorithm Find feedback arc set and cut from the circuit
Convert every gate into dual-rail encoded ternary logic
Encoded every PI into dual-rail scheme
Add dummy variables at every cut location
Set up an equivalence checker for every pair of dummy variables
Set up a -checker for every pair of dummy variables

15. SAT Circuits Equivalence checking -checker
Is true ↔ the value assigned to dummies = the value computed by the circuit at the cut location
Reach a fixed point
-checker
Is true ↔ one pair of dummy variables is

16. Example: Break the Feedback Arc

17. Example: SAT Circuit

18. Proof of Correctness Satisfiable → Invalid Invalid → Satisfiable
g1 = 1, value in the circuit are at a fixed point
g2 = 1, some of values are
Invalid → Satisfiable
Has some values at a fixed point
g1 = 1
g2 = 1

19. Experimental Results

20. Discussion
Feedback provides significant opportunities for optimization
Cyclic solutions are not a rarity
SAT-based method is faster than BDD-based

21. Future Work
Develop specific heuristics for finding smaller feedback arc sets
Integrate SAT-based analysis with synthesis