1. Lecture 14 – Operand addressing (cont.) Microcode & Modes
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

2. Announcements Sample midterms posted on website
Lab 02 grading complete
Homework and lab solutions are (and have been) available on Blackboard
Homework 3 posted, due next Wednesday 7/5 11:58pm
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

3. Midterm information Monday July 3, 8:30-9:30am in MATH 175
Seating chart available soon
Test conditions
Closed book, no notes, no calculator
Necessary reference figures, etc. included in exam
30-40 questions
Bring PU ID, several #2 pencils, and an eraser
Only questions related to typographical or semantic errors will be answered
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

4. Midterm Textbook chapters 1-9 Labs 00-04 Homeworks 01-03
Only portions relevant to what has been covered in lecture so far
Labs 00-04
Homeworks 01-03
Lectures 01-14
Last bit of content today
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

5. ISAs with dedicated instr. for mem access
0-address and Reg-Reg, a.k.a Load/Store, architectures have instructions specifically to read/write computer memory
3-address
Reg-Mem
Architecture
Reg-Reg/
Load-store Arch.
ALU …
Processor
Top of
Stack
Memory
0-address
Stack architecture
1-address
Accumulator
Stack
Accum-ulator
Reg file
Push
Pop
Load
Store
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

6. ISAs with dedicated instr. for mem access
0-address and Reg-Reg, a.k.a Load/Store, architectures have instructions specifically to read/write computer memory
Reg-Reg/
Load-store
ALU …
Processor
Top of
Stack 
Stack
Accumulator
Reg-Mem
Accum-ulator
Reg file
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

7. Code for C=A+B for 0-, 1-, and 3-addr.
Assumes A, B, C all belong in memory and that A, B not destroyed
Reg-Reg/
Load-store
ALU …
Processor
Top of
Stack 
Stack
Accumulator
Reg-Mem
Accum-ulator
Reg file
Memory C B A C B A C B A C B A
Push A
Push B
Add
Pop C
Load A
Add B
Store C
Load R1,A
Add R4,R1,B
Store C,R4
Load R1,A
Load R2,B
Add R4,R2,R1
Store C,R4
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

8. Sources of operands
Immediate operand – the field in the instruction bit string contains the actual bit string of the operand (the operand value)
Called “immediate” because there is immediate access to the operand value for execution
Register – pointed to by an instruction field
Memory – a memory address is, typically, too many bits to fit within a field within an instr.
Pointer to in-memory operand will be computed
Memory is slow these days, so we source operands from memory only when we must
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

9. Example operand addressing modes (Fig. 7.6)
Thought question
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

10. Von Neumann bottleneck
Memory technology today is slow compared to execution speed of a processor circuit
Circuit consumes operands and produces results far faster than current technology can readily source and sink
Time spent accessing memory often dominates the total time to run a program
Architects use the term von Neumann Bottleneck to describe the situation when memory access time is majority of run time
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

11. Design tradeoffs for operands
Different operand sources and forms have different
Ease of programming/compiling
Fewer/more machine instructions
Smaller/larger machine instructions
Larger/smaller range of immediate values
Faster/slower operand fetch
Larger/smaller processor circuit size
There is not one right answer
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

12. Summary Operand types and addressing are design choices
Immediate operands are constants contained within the instruction
Pointers to registers (smaller) and memory (often too large) are used in instructions
Can obtain operands via indirection
Register contains an address to memory
A memory location contains an address to memory
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

13. Microcode & Modes © 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

14. © 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

15. Fast forward to today
Hardware ~106 cheaper, ~1010 more reliable than it was in the 1960’s (pre-Moore’s Law)
So design complex circuits
Multiple cores
Multiple roles
Protection/privilege and priority
Larger basic data and address size (64-bit)
High performance (run-time optimization)
Broadest possible user base desired
Cannot expose the entire system to most users
Too confusing; too risky
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

16. Execution modes CPU hardware has several possible modes
At any time, CPU operates in one mode
Mode sets various parameters, including, but not limited to
Privilege level
Which instructions of the ISA are valid
Which addresses are valid
Size of data items
Backward compatibility with earlier ISAs
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

17. How to think about modes
Imagine different CPUs inside a given CPU
Mode selects which CPU is currently in use
Two modes may have different
Numbers of registers
Register size
Instruction sets
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

18. How to change between modes
Automatic change (hardware does its thing)
Initiated by hardware: example, an Input/Output (I/O) device needs service
Prior to changing mode, operating system (OS) specifies the new mode
“Manual” change (under program control)
Initiated by software, typically the OS
Typical example, application program calls an OS function
Some modes can be selected by an application
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

19. Privilege and protection
Number of privilege levels is a design choice: 0 through 8 have been built
Levels limit operations allowed so CPU can detect “unauthorized operations”
Example, I/O device service (printing)
CPU must allow device driver software in the OS to interact with the I/O device
Applications must not be allowed to do this
Erroneous or malicious commands to I/O device are dangerous
Halt and Catch Fire story here
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

20. Microcoded instructions
How should a CPU be implemented?
One way is totally in hardware, another is to combine a simpler circuit and stored code
Microprocessor provides basic instructions
Stored code implements “macro” instructions built out of basic instructions and offers additional, more sophisticated capabilities
Key idea: can add complex instructions (macro) more easily via code than circuitry
Change stored code to allow field upgrades
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

21. CPU with microcode © 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

22. 32-bit ADD32 macro for 16-bit circuit
Figure 8.4 01 02 03 04 05 06 07 08 09 10 11
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

23. Microcode pro and con Pro Con Fast update of a processor
Errors easy to correct
Microcode usually hidden from programmers
Con
Execution overhead: macro instructions take multiple clock cycles
Microcode usually hidden from programmers; when not hidden, CPU is called “reconfigurable”
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

24. Vertical and horizontal microcode
Vertical microcode uses a full-featured, small microcontroller and then builds macro instructions on top of this foundation
Example, x86 uses a small ARM-like RISC microcontroller inside and lots of vertical microcode to implement CISC instructions of x86
One macro instruction usually requires several to many micro-instructions
Horizontal microcode programs on all the circuitry functions units of the bare metal
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

25. Horizontal microcode format
Horizontal microcode is programming the control signals that are abstracted out of Figure 6.9, for example
A memory can be used to implement any Boolean logic function
Each memory address bit becomes one of the Boolean logic function inputs
Each memory location then holds all the logic function output bits for a single truth table product term in an SOP implementation
“Computing” the Boolean function transformed into “look up the pre-computed answer”
Not uncommon for instructions to be large – 100 bits or more
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

26. Horizontal microcode characteristics
Can expose more parallelism potential in the processor circuit
Example: an ALU operation that takes more than one clock cycle to complete
Operands coming from fast register unit finish during the first clock cycle
Register unit could sit idle, or perhaps could service other operations while multi-cycle operation executes
More work simultaneously means all work of a program may be completed sooner
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

27. Field-programmable gate array (FPGA)
FPGA chip contains a regular array of logic devices and a grid of interconnections, something like every input to every gate
FPGA is “programmable” with a “burner”
Design a circuit that can be mapped onto a subset of the logic and connection grid, then
“Burn,” or blow out the unneeded connections
Some FGPAs can be burnt once, some can be “cleared” and burned to a new circuit
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

28. Summary CPU modes determine protection and privilege
CISC usually implemented with microcode
Vertical microcode uses a conventional- looking code (like assembly for a simpler CPU)
Horizontal microcode looks like complex Boolean logic functions
Horizontal microcode offers more parallelism
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

29. Map fetch-execute cycle onto circuit
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

30. Fetch an instruction and compute the Default_Next_Instruction_Pointer
Fetched
instruction
Current_Instruction_Pointer 
 Default_Next_ Instruction_Pointer
Fetch using Current_Instruction_Pointer, also known as (a.k.a.) the Program Counter
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

31. Fetch, then Decode instruction, access operands, and sign extend
Decode by separating instruction fields as groups of wires. Then point to and access registers and sign extend regardless of opcode.
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

32. Fetch, Decode, then Execute instruction
Sign extend
ALU and M2 control inputs are functions of Opcode field bits
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra

33. Fetch, Decode, Execute, access Data Mem
Sign extend
Data Memory always receives Addr._In and Data_In bit strings. Abstracted READ_Enable (RE) and WRITE_Enable (WE) Data Memory control signals are functions of Opcode. Data Memory reads at Addr._In if RE = true, writes Reg_B_Value at Addr._IN if WE = true, and does nothing if RE = WE = false.
© 2017 by George B. Adams III

34. Fetch, Decode, Execute, Mem, Write Back
Sign extend
Bit strings from all sources of results are routed by M3 and M1 to the appropriate destination register (32-bit pgm. ctr. is a register). M3 and M1 control signals are functions of the Opcode.
© 2017 by George B. Adams III
Portions © 2017 Dr. Jeffrey A. Turkstra