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Noise measurements on 65 nm CMOS transistors at very high total ionizing dose
V. Rea,c, L. Gaionia,c, L. Rattib,c, E. Riceputia,c, M. Manghisonia,c, G. Traversia,c
aUniversità di Bergamo
Dipartimento di Ingegneria e Scienze Applicate
bUniversità di Pavia
Dipartimento di Ingegneria Industriale e dell’Informazione
cINFN Sezione di Pavia
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Motivation
65 nm CMOS technology is a candidate for mixed-signal readout of high granularity silicon pixel sensors, with potential to meet the requirements of diverse applications such as particle tracking in the innermost layers of ATLAS and CMS at HL-LHC and photon imaging at very high brilliance and high rate light sources
Tolerance to extremely high levels of ionizing radiation is a key requirement for both application fields, up to 1 Grad Total Ionizing Dose (TID) during chip lifetime.
RD53 collaboration has carried out an extensive study of the behavior under irradiation of a 65 nm CMOS technology, with which a first generation of demonstrator chips is being designed
The goal of this paper is to find out if 65 nm CMOS analog front-end circuits can still provide an adequate noise performance even at extremely high total doses. Study of radiation effects on noise can give very important hints about damage mechanisms.
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3. Test devices and irradiation procedure
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Test devices and irradiation procedure
A test chip was submitted and fabricated with the TSMC 65 nm LP CMOS process, including NMOS and PMOS transistors (standard interdigitated layout) with W in the range 0.12 – 600 µm, L in the range 65 – 700 nm
NMOS and PMOS transistors were irradiated with 10-keV X-rays from a 50 kV X-ray machine at INFN Laboratori Nazionali di Legnaro (Italy) and at CERN, with a dose rate of 2 krad(SiO2)/s
MOSFETs were biased during irradiation in the worst-case condition, that is, with all terminals grounded, except the gate of the NMOS, which was kept at VDD = V
Irradiation and following measurements were performed at room temperature. During the time between irradiation and measurements, the devices were kept at about 0 °C to prevent annealing effects
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4. 65 nm CMOS at extreme radiation levels
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65 nm CMOS at extreme radiation levels
At the HL-LHC design luminosity, for an operational lifetime of 10 years, the innermost pixel layer will be exposed to a total ionizing dose of 1 Grad, and to an equivalent fluence of 1-MeV neutrons of 2 x 1016 n/cm2.
If unacceptable degradation, a replacement strategy must be applied for inner pixel layers.
Nanoscale CMOS (with very thin gate oxide) has a large intrinsic degree of tolerance to ionizing radiation: what happens at 1 Grad?
Radiation induced electric charge is associated with thick lateral isolation oxides
What is the effect on the noise performance of the transistors?
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Operating region
Under reasonable power dissipation constraints, a 65 nm CMOS transistor used as a preamplifier input device will operates in the weak inversion region
Operating point for W/L =400/0.2 (strips), ID = 40 mA
W/L =20/0.1 (pixels), ID = 4 mA
μ carrier mobility
COX specific gate oxide capacitance
VT thermal voltage
n proportional to ID(VGS) subthreshold characteristic
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6. CMOS generations from 250 nm to 65 nm
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Noise in NMOS:
CMOS generations from 250 nm to 65 nm
1/f noise has approximately the same magnitude (for a same WLCOX) across different CMOS generations. White noise has also very similar properties (weak/moderate inversion).
1/f noise
kf 1/f noise parameter
αf 1/f noise slope-related coefficient
Channel thermal noise
kB Boltzmann’s constant
T absolute temperature
αw excess noise coefficient
γ channel thermal noise coefficient
In weak inversion:
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7. 65 nm LP process: 1/f noise in NMOSFETs
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65 nm LP process: 1/f noise in NMOSFETs
The 1/f noise parameter Kf does not show dramatic variations across different CMOS generations and foundries.
kf 1/f noise parameter
αf 1/f noise slope-related coefficient
( 0.85 in NMOS,  1 – 1.1 in PMOS)
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8. 65 nm LP process: 1/f noise in PMOSFETs
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65 nm LP process: 1/f noise in PMOSFETs
In the 65 nm LP process, NMOS and PMOS have similar 1/f noise (especially longer transistors), which did not happen in previous CMOS generations
This could be explained by a “surface channel” behavior for both devices, and/or by the fact that gate dielectric nitridation decreases the barrier energy experienced by holes across the silicon-dielectric interface. This would make it easier for the PMOS channel to exchange charges with oxide traps.
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9. Ionizing radiation effects in sub-100 nm CMOS
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Ionizing radiation effects in sub-100 nm CMOS
Radiation induced positive charge is removed from thin gate oxides by tunneling (which also prevents the formation of interface states)
Isolation oxides remain thick (order of 100 nm) also in nanoscale CMOS, and they are radiation soft.
With scaling, the effect of positive charge buildup in STI oxides appears to be mitigated by the higher doping of the silicon bulk.
However, the radiation-induced noise degradation may be sizable, especially in NMOSFETs. This is associated to noisy lateral parasitic transistors.
At high doses, radiation-induced interface states associated with STI oxides may play an important role: they trap negative charge in the case of NMOSFETs, positive charge in the case of PMOSFETs
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10. NMOSFETs and lateral leakage
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NMOSFETs and lateral leakage
In NMOSFETs edge effects due to radiation-induced positive charge in the STI oxide generate sidewall leakage paths.
Shaneyfelt et al,
“Challenges in Hardening Technologies using Shallow-Trench Isolation”
IEEE TNS, Dec. 1998 L
Lateral transistors have the same gate length as the main MOSFET
NMOS finger
Drain
Multifinger NMOS
STI mf 1 2 n+
Gate
Drain
poly
Gate
Source
Source n+
STI
Lateral parasitic
devices
Main transistor
finger
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11. Modeling lateral leakage in NMOSFETs
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Modeling lateral leakage in NMOSFETs
Radiation induced positive charge trapped in STI oxides may turn on lateral parasitic transistors. Initially, with increasing dose a larger and larger portion of the STI sidewall gets inverted.
The effective gate width, oxide thickness and capacitance are determined by the extension of the inverted regions along sidewalls.
At first, only the sidewall bottom is inverted because bulk doping is lower in that region; at increasing TID, the inversion region extends towards the surface, involving thinner STI oxide regions.
At higher doses, negative charge trapped at interface states compensates positive oxide charge, and then may even become dominant
Main transistor
finger
Source
Drain
Gate
Lateral parasitic
devices
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12. Total ionizing dose effects on noise in LP 65 nm CMOS
Main transistor
(gate oxide)
Equivalent parasitic transistor
(STI oxide)
V. Re, M. Manghisoni, L. Ratti, V. Speziali, G. Traversi: "Impact of lateral isolation oxides on radiation-induced noise degradation in CMOS technologies in the 100-nm regime”, IEEE Trans. Nucl. Sci., vol. 54, no. 6, December 2007, pp
V. Re, L. Gaioni, M. Manghisoni, L. Ratti, G. Traversi: “Mechanisms of noise degradation in low power 65 nm CMOS transistors exposed to ionizing radiation”, IEEE Trans. Nucl. Sci., vol. 57, no. 6, December 2010, pp
A model (which worked well at 10 Mrad TID) for the contribution of lateral parasitic transistors to the total noise of an irradiated NMOS can be based on the following equations:
White noise
1/f noise

13. NMOSFETs LP 65 nm technology – 10 Mrad
Moderate 1/f noise increase at low current density, due to the contribution of lateral parasitic devices
At higher currents the degradation is almost negligible because the impact of the parasitic lateral devices on the overall drain current is much smaller
No increase in the white noise region is detected

14. NMOSFETs – up to 600 Mrad low current density
Moderate 1/f noise increase, no increase in the white noise region is detected
The behavior as a function of the current density is different at high TID, as compared to 10 Mrad
At 200 Mrad (and even 600 Mrad), at low ID 1/f noise increase with respect to pre- irradiation values is smaller than at 10 Mrad

15. NMOSFETs – up to 600 Mrad low current density
At 200 Mrad (and even 600 Mrad), at low ID 1/f noise increase with respect to pre-irradiation values is smaller than at 10 Mrad
This can be correlated with the evolution of radiation effects at increasing TID and with the behavior of ID vs VGS

16. medium current density
NMOSFETs – up to 600 Mrad
medium current density
At higher currents, 1/f noise increases by approximately the same amount as at smaller currents when the device is exposed to 200 Mrad and 600 Mrad TID

17. NMOSFETs – up to 600 Mrad high current density
At higher currents, 1/f noise increases by approximately the same amount as at smaller currents when the device is exposed to 200 Mrad and 600 Mrad TID

18. NMOSFETs – up to 600 Mrad high current density
At higher currents, 1/f noise increase at 10 Mrad is slightly smaller than at 200 Mrad

19. NMOSFETs – 1/f noise coefficient
The effect of 1/f noise increase can be nonnegligible: at 600 Mrad the 1/f noise coefficient increases by about a factor 3 at low currents
(70% increase of the contribution to the ENC of a detector readout channel)
A possible explanation of this behavior is that at very high doses negative charge trapped in interface states at the STI oxides gradually compensates oxide- trapped positive charge, switching off lateral parasitic transistors
Noise contributions by these parasitic devices become less important; 1/f noise increase from 200 Mrad to 600 Mrad can be explained by other effects (increase of border traps in gate oxides, defects in spacer dielectrics…)

20. NMOSFETs – ID vs VGS
No sizable effects can be seen in devices with large W/L, except in the leakage current region.
But looking at these data in more detail, it is possible to see interesting effects that may be correlated with the behavior of noise in irradiated devices.

21. NMOSFETs – ID vs VGS
ID vs VGS curves appear to shift in different directions, moving to the left at 10 Mrad, and then to the right at 200 and 600 Mrad .

22. NMOSFETs – ID variation
At low TID, positive charge in STI oxides switches on lateral devices, increasing ID (for the same VGS)
At higher doses negative charge trapped in interface states at the STI oxides gradually compensates oxide-trapped positive charge, switching off lateral parasitic transistors and reducing ID (for the same VGS)

23. NMOSFETs – ID variation
At low TID, positive charge in STI oxides switches on lateral devices, increasing ID (for the same VGS)
At higher doses negative charge trapped in interface states at the STI oxides gradually compensates oxide-trapped positive charge, switching off lateral parasitic transistors and reducing ID (for the same VGS)

24. Threshold shift
This is confirmed by the behavior of the radiation- induced threshold shift, which in NMOSFETs is negative at 10 Mrad and positive at 200 Mrad and 600 Mrad.
Because of the effect of interface states, ID vs VGS curves are also stretched at high TID.

25. PMOSFETs – 1/f noise – low current density
Again no effect is detected in the white noise region, while 1/f noise moderately increases.
Lateral parasitic devices do not play a role here (positive charge is accumulated both in oxides and at interface states), so there is no dependence on the drain current density

26. PMOSFETs – 1/f noise – high current density

27. PMOSFETs – 1/f noise coefficient
The effect of 1/f noise increase can be nonnegligible: at 600 Mrad the 1/f noise coefficient increases by about a factor 2
(40% increase of the contribution to the ENC of a detector readout channel)

28. PMOSFETs – ID vs VGS
ID vs VGS curves appear to shift in the same direction (to the left) at 5 Mrad (very slightly), and then at 200 and 600 Mrad .

29. PMOSFETs – ID variation

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Ionizing radiation effects on the signal-to-noise ratio in a pixel readout channel
The noise data reported here can provide the basis to estimate the performance of an analog front-end for pixel detectors at extremely high TID
Even at a signal peaking time of 25 ns, the impact of the radiation-induced 1/f noise increase can be sizable in the bandwidth of an analog channel
This plot shows the noise voltage spectrum of an NMOS with W/L =20/0.13, before irradiation and at 600 Mrad TID, calculated using data extracted from measurements
The transfer function of an RC2-CR semigaussian shaper with 25 ns peaking time is superimposed to the spectra
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Conclusions
A complete analysis of the measurements reported here can provide a model for the noise behavior of 65 nm CMOS transistors at extremely high TID
The performance of analog front-end channels for pixel detectors as a function of TID can be forecasted on the basis of this model and compared with experimental results
Design criteria for low-noise performance at high TID can also be derived from these data
This work is still in progress, and will benefit from the study of ionizing radiation damage mechanisms in 65 nm CMOS transistors that is being carried out by the RD53 Radiation Working Group
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Backup slides
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65 nm NMOS: white noise
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34. 65 nm LP process: gate current
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65 nm LP process: gate current
In the 65 nm technology, different process flavours are available with various power and performance.
We made tests on LP (Low Power) transistors (VDD = 1.2 V). These devices were optimized for a reduced leakage (larger equivalent oxide thickness, different level of nitridation with respect to other flavours, different silicon stress ).
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35. NMOSFETs – ID variation

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1/f noise: NMOS vs PMOS
In bulk CMOS, the fact that PMOSFETs feature a smaller 1/f noise with respect to equally sized NMOSFETs was generally related to buried channel conduction.
In deep submicron processes, it was expected that the PMOS would behave as a surface channel device, rather than a buried channel one as in older CMOS generations.
With an inversion layer closer to the oxide interface, 1/f noise is expected to increase. Ultimately, PMOSFETs should feature the same 1/f noise properties as NMOSFETs. However, this was not observed in CMOS generations down to 130 nm and 90 nm.
A possible interpretation can be related to the different interaction of electrons (NMOS) and holes (PMOS) with traps in the gate dielectric (different barrier energies experienced by holes and electrons across the Si/SiO2 interface) .
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