1. Synthesis Design Team Henry Leung, Jizhou Li
Buffer 1
Synthesis Design Team
Henry Leung, Jizhou Li

2. Run Synopsis Design Compiler
# HDL file names (.v or .vhd) #
set my_HDL_files [list fofo.vhd txt_util.vhd]
# Top-level Module / Entity name #
set my_toplevel fifo_read
# The name of the clock pin #
# If no clock-pin exists, pick anything #
set my_clock_pin clk
# Target frequency in MHz for optimization #
set my_clk_freq_MHz 100
# Delay of input signals (Clock-to-Q, Package etc.)#
set my_input_delay_ns 0.1
# Reserved time for output signals (Holdtime etc.) #
set my_output_delay_ns 0.1
####################################################
# No modification below #

3. Initial Timing Report # generated on Fri Jan 21 15:26:21 2011
# Top Cell: fifo_read
timeDesign Summary
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
| WNS (ns):| | | | | N/A | N/A |
| TNS (ns):| | | | | N/A | N/A |
| Violating Paths:| | | | | N/A | N/A |
| All Paths:| | | | | N/A | N/A |
| | Real | Total |
| DRVs |
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
| max_cap | (247) | | (247) |
| max_tran | (0) | | (0) |
| max_fanout | (0) | | (0) |
Density: %
Routing Overflow: 0.00% H and 1.53% V

4. Post CTS Timing Report # generated on Fri Jan 21 15:30:55 2011
# Top Cell: fifo_read
timeDesign Summary
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
| WNS (ns):| | | | | N/A | N/A |
| TNS (ns):| | | | | N/A | N/A |
| Violating Paths:| | | | | N/A | N/A |
| All Paths:| | | | | N/A | N/A |
| | Real | Total |
| DRVs |
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
| max_cap | (247) | | (247) |
| max_tran | (0) | | (0) |
| max_fanout | (0) | | (0) |
Density: %

5. Post-Route Timing Report
# generated on Fri Jan 21 15:35:
# Top Cell: fifo_read
timeDesign Summary
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
| WNS (ns):| | | | | N/A | N/A |
| TNS (ns):| | | | | N/A | N/A |
| Violating Paths:| | | | | N/A | N/A |
| All Paths:| | | | | N/A | N/A |
| | Real | Total |
| DRVs |
| | Nr nets(terms) | Worst Vio | Nr nets(terms) |
| max_cap | (250) | | (250) |
| max_tran | (0) | | (0) |
| max_fanout | (0) | | (0) |
Density: %

6. Connectivity Verify ******** Start: VERIFY CONNECTIVITY ********
Start Time: Fri Jan 21 15:38:
Design Name: fifo_read
Database Units: 2000
Design Boundary: (0.0000, ) ( , )
Error Limit = 1000; Warning Limit = 50
Check all nets
VC Elapsed Time: 0:00:00.0
Begin Summary
Found no problems or warnings.
End Summary
End Time: Fri Jan 21 15:38:
******** End: VERIFY CONNECTIVITY ********
Verification Complete : 0 Viols. 0 Wrngs.
(CPU Time: 0:00:00.1 MEM: 0.031M)

7. Geometry Verify
encounter 1> *** Starting Verify Geometry (MEM: 325.2) ***
VERIFY GEOMETRY Starting Verification
VERIFY GEOMETRY Initializing
VERIFY GEOMETRY Deleting Existing Violations
VERIFY GEOMETRY Creating Sub-Areas
bin size: 2080
VERIFY GEOMETRY SubArea : 1 of 1
VERIFY GEOMETRY Cells : 0 Viols.
VERIFY GEOMETRY SameNet : 0 Viols.
VERIFY GEOMETRY Wiring : 0 Viols.
VERIFY GEOMETRY Antenna : 0 Viols.
VERIFY GEOMETRY Sub-Area : 1 complete 0 Viols. 0 Wrngs.
VG: elapsed time: 0.00
Begin Summary ...
Cells : 0
SameNet : 0
Wiring : 0
Antenna : 0
Short : 0
Overlap : 0
End Summary
Verification Complete : 0 Viols. 0 Wrngs.
**********End: VERIFY GEOMETRY**********
*** verify geometry (CPU: 0:00:00.4 MEM: 13.5M)

8. Layout

9. ModelSim Simulation with original VHDL file
Simulation with synthesized VHDL file