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EEE2135 Digital Logic Design Chapter 1. Introduction

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1 EEE2135 Digital Logic Design Chapter 1. Introduction
서강대학교 전자공학과

2 1. Digital vs. Analog System
Basics Discrete vs. continuous mixed (hybrid) systems ADC and DAC Binary /Digital Systems Most information processing systems are constructed from switches Decision making process for digital systems Immune to noise, more reliable Switches Mechanical switches Semiconductor switches

3 ADC Analog Signal - Continuous both in time and magnitude Sampling
- Sample signal at discrete times - Nyquist theorem can be applied (Original signal can be restored if the sample rate exceeds 2 fmax) Quantization and Digitization - Convert into discrete values and then into binary numbers - How many bits required ? It determines accuracy and error Ex. 2 bits employed for a signal value representation: allows 4 (= 22) different values, max error = M/2(22-1) if n bits employed: allows 2n different values, max error = M/2(2n-1)

4 DAC Rf R0 R3 R2 R1 v3 v2 v0 v1 vout + - Vout = - { (Rf/R0)v0 + (Rf/R1)v1 + (Rf/R2)v2 + (Rf/R3)v3 } If R0 = Rf, R1 = Rf/2, R2 = Rf/4, R3 = Rf/8 Vout = - { v0 + 2v1 + 4v2 + 8v3 } = - {20v0 + 21v1 + 22v2 + 23v3 } OP Amp

5 … Analog signal Frequency spectrum FT Sampling Repeated pattern
fmax FT Sampling Repeated pattern Sampled signal Frequency spectrum t A DFT f F fmax fsample … -fmax

6 2. Behavior and Structure
Behavioral Description Functionality, input/output relationships Truth table, equation, HDL Structure Description Functional modules (components) and their interconnections Block diagrams Schematic diagrams - generic block symbols replaced by symbols with distinctive/standardized shapes

7 3. Digital System Design Design
Refinement process from behavior to structure Specification to implementation Synthesis (by automated software) Design levels Designs described at various levels of details or complexity Design hierarchy - A non-primitive component Ci at level i can be expanded to a multi-component system at level i-1 Hierarchical design reduce design complexity to partition system into subsystems with manageable size To allow concurrent design by team members To use reusable components (libraries)

8 Top-down vs Bottom-up Design Process
a. Design abstraction levels architectural level register-transfer level logic/gate level circuit level physical level b. Design Implementations - Depending upon volumes (total # chips) - Full-custom design (using standard cell) - Semi-custom design (ASIC, gate-array, sea-of-gates) - Off-the-shelf components (FPGA) Top-down design Bottom-up design

9 3) Design Implementation
Cost Full-Custom: Huge NRE cost (CNRE= $수백만) CFC = CNRE/N + wafer production cost/n, n = #chips per wafer , N = total #chips to be produced Semi-custom: Less NRE cost (CNRE’= $수만 ~ $ 수십만) CSC = CNRE’/N’ + wafer production cost/n’, n’ = #chips per wafer , N’ = total #chips to be produced FPGA : No NRE cost CFPGA = $수십~$수백/chip * Price depends on #gates in a chip Performance FC > SC > FPGA in speed FC < SC < FPGA in area

10 A field-programmable gate array chip (courtesy of Altera Corp.)
Group of 8 logic cells Memory block Interconnection wires A field-programmable gate array chip (courtesy of Altera Corp.)

11 4. Digital Systems and Digital Circuits
Datapath data storage data transformation data transfer Controller Hardwired Two-level logic (PLA) Multi-level logic Microprograms Computer system hierarchy Application Software (DBMS) System Software, Utilities OS Instruction set Architecture Hardware

12 Digital Circuits Combinational circuits
Outputs determined by current inputs structure : two-level and multi-level logic Sequential circuits outputs depends not only on current inputs but also on past inputs (stored in the form of ‘state’) model Comb. circuit Memory 소자 Inputs X Y Outputs Z Y+

13 5. Design goals Design Goals
Functional specifications Implementation (after simulation / verification) Cost and Performance Area Delay(Latency) : Speed, frdequency Power Consumption Access time (Storage elements) Bandwidth (Especially for busses) Testability Reliability Design Trade-offs Cost/performance trade-offs Engineering experiences Refinement

14 6. Computer-Aided Design
CAD Tools Editor/Schematic capture Simulators at various levels System level Instruction-set level Architectural level Logic level Switch level Circuit level Device level Process level Synthesizer Block level

15 Design Descriptions Netlists Equation, tt, pla formats
Hardware Description Languages Verilog HDL VHDL SystemC

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