1. Overview of Architecture Assembly Programming Concepts
Embedded Systems Programming
Overview of Architecture
and
Assembly Programming Concepts

2. AVR Architecture Overview Instruction execution Registers
Contents
AVR Architecture Overview
Instruction execution
Registers
Addressing modes (will be covered in brief)
Status register and Flags
Stack pointer

3. AVR Architecture Overview – Simplified block diagram
There is a wide variety of I/O logic and
ports to enable very flexible interfacing
to the monitored / controlled system.
I/O
The heart of the microcontroller is a
CPU. This executes instructions and
controls the other functional blocks.
CPU
The address, data and control busses
enable the various functional blocks to
communicate.
Address / data / control
Clocks /
Timing
Various clock sources and timer options
are provided.
On-chip memory simplifies deployment
and enables fast access.
Memory 3
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

4. AVR Architecture Overview – Device family
There are four general groups of AVR devices:
tinyAVRs: 1-8 kB program memory,
8-32-pin package,
Limited I/O support.
megaAVRs: kB program memory,
pin package,
Larger instruction set (e.g. Multiply, and special instructions
for addressing larger program memories),
Extensive I/O support .
XMEGA: kB program memory, pin package,
Enhanced performance (e.g. DMA and cryptography),
Extensive I/O support, including DAC.
Application specific AVRs:
These are megaAVRs with special in-built features including:
LCD controller; USB controller; advanced PWM; CAN support
(Controller Area Network) etc.
Further information is available at:
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

5. Instruction execution
The AVR instructions are mostly very simple and mostly execute in a single clock cycle.
The current instruction execute and the next instruction fetch are performed in parallel.
This has several impacts:
Approximately 1 MIP per 1 MHz is achieved,
Execution timing calculations / predictions for code are much simpler. 5
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

6. The General Purpose Registers
There are 32 8-bit general purpose registers: R0 – R31 (data value )
Sometimes these are used in pairs to make a 16-bit register, written as
Rn+1:Rn (where Rn+1 holds the upper byte and Rn holds the lower byte).
(data value 0 – 65535; 0x00:0x00 - 0xFF:0xFF; e.g. 0x04:0x00 = 1024)
The ALU is designed for register contents manipulation, thus all destination operands (and many source operands) are registers.
Most instructions behave the same for all registers, but there are some instructions which only work with a subset, some examples include:
Instruction Register subset
Adiw, Sbiw R24:R25, R26:R27, R28:R29, R30:R31
Andi, Cpi, Ldi, Muls R16 – R31
Spm R1:R0 6
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

7. Instruction syntax, coding format and memory image (RJMP example)
Actual instruction is RJMP 0x020
(The .org 0x020 directive places the ‘INIT’ label at program address 0x020)
Actual offset is 0x01F program memory places because the PC is already pointing to the instruction address after the current one (which is address 0x001).
So RJMP 0x020 is coded as:
Program address 0x020 is actual memory address 0x040 because each program address must hold an instruction (2 bytes each).
Upper byte = 0xC0 Lower byte = 0x1F

8. Addressing Modes – Overview
‘Addressing Mode’ refers to the way in which the operands are provided to an instruction, and the way they are used.
Key terms:
‘Immediate’ - a constant numeric value,
‘Direct’ - the value held in a register,
‘Indirect’ - the contents of one or more registers are used to provide
the address of the data value,
‘Offset’ or ‘Displacement’ - a value added to an address stored in a
register, to provide an index to the data.
There are four classes of addressing supported by the AVR:
Register addressing – direct manipulation of register contents,
Data addressing – storage / retrieval of data values (SRAM, including
to/from the general purpose registers),
Program Memory addressing – reading writing to Flash or EEPROM,
I/O addressing – access to the special registers for I/O and
configuration of peripheral controllers. 8
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

9. Addressing Modes – Special roles of General Purpose registers
Six of the general purpose registers are also used to support the indirect addressing modes.
For this purpose they are organised as three pairs, X, Y and Z (each 16 bits).
X = R27(upper byte): R26(lower byte)
Y = R29(upper byte): R28(lower byte)
Z = R31(upper byte): R30(lower byte) 9
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

10. Addressing Mode – Register Direct (single register Rd)
The operation acts on the register specified, without further operands.
Only 32 registers are supported, hence the Rd operand is only 5 bits.
Examples:
Inc R17
Clr R18
8-bit Register
Direct
update 10
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

11. Addressing Mode – Register Direct (two registers Rd and Rr, or
one register and an 8-bit immediate value)
The operation acts on the two registers specified, without further operands.
Examples:
Add R12,R15
Or R17, R23
Ldi R16, 0xFF
Number
8-bit Register 11
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

12. Addressing Mode – I/O Direct
The operation acts on the register specified and the I/O address specified.
Only 64 I/O addresses are supported, hence the ‘A’ operand is only 6 bits.
(Note: in the examples below, the I/O address is specified by the I/O register
name which is defined in the microcontroller-specific include file).
Examples:
In R18, PIND
Out PORTA, R22
I/O address or Port
8-bit Register 12
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

13. Addressing Mode – Data Direct
The operation acts on the register specified and the 16-bit data-space address specified.
Examples:
Lds R18, 0x0100
(Load direct from data space)
Sts 0x0101, R22
(Store direct to data space)
Number
Address Memory location
8-bit Register
Number
Address Memory location
8-bit Register 13
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

14. Addressing Mode – Data Indirect
The operation moves data between the register specified and the 16-bit data-space address specified by either X, Y or Z.
X, Y, or Z is left unchanged.
Examples:
St X, R16 (register X: R27 = high, R26 = low)
As in: Ldi R27, 0x00
Ldi R26, 0x68
Ldi R16, 0x81
St X, R16
16-bit Register
Address Memory location
8-bit Register
Address Memory location
8-bit Register
16-bit Register 14
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

15. Addressing Mode – Data Indirect with Displacement
Moves data between the register specified and the 16-bit data-space address specified by either Y or Z, plus the displacement.
Y or Z is left unchanged.
Examples:
Std Y+1, R17
(Y: R29=high, R28=low)
As in: Ldi r29, 0x00
Ldi r28, 0x70
Ldi R17,0x18
Std Y+1, R17 (displacement is 1 in this example)
16-bit Register
+ Number
Address Memory location
8-bit Register
Address Memory location
8-bit Register
16-bit Register
+ Number 15
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

16. Addressing Mode – Data Indirect with Pre-decrement
The operation moves data between the register specified and the 16-bit data-space address specified by either X, Y or Z, minus 1.
X, Y or Z is decremented before the data access occurs.
Example:
St -Z, R18
As in:
Ldi r31, 0x01
(Z: R31=high, R30=low)
Ldi r30, 0x7F
(will count down from
this address)
Ldi R18, 0x55
(store in address 0x017E)
16-bit Register
Address Memory location
8-bit Register --
Address Memory location
8-bit Register
16-bit Register -- 16
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

17. Addressing Mode – Data Indirect with Post-increment
The operation moves data between the register specified and the 16-bit data-space address specified by either X, Y
or Z.
X, Y or Z is incremented after the data access occurs.
Example:
St Z+, R19
As in:
Ldi r31, 0x02
(Z: R31=high, R30=low)
Ldi r30, 0x40
(will count up from this
address)
Ldi R19, 0xA4
(store in address 0x0240)
16-bit Register
Address Memory location
8-bit Register ++
Address Memory location
8-bit Register
16-bit Register ++ 17
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

18. Signed and Unsigned arithmetic
An 8-bit register contains a value between 0 and 255
Unsigned - the full range 0 – 255 is required (assumed +ve values)
0b = 1
0b = 127 (128 – 1)
0b = 192 ( )
0b = 129 ( )
Signed – first bit holds sign bit, remaining 7 bits hold value
0b = +1 (sign bit is positive)
0b = (sign bit is positive)
0b = -9 (sign bit is negative)
0b = (sign bit is negative)
To generate a 2’s complement number, invert all the bits and add 1
+1 is 0b is 0b b = 0b
+2 is 0b is 0b b = 0b
+5 is 0b is 0b b = 0b
+127 is 0b is 0b b = 0b
To ‘un-convert’ a 2’s complement number, invert all the bits and add 1
-5 is 0b is 0b b = 0b
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich 18

19. Half-carry, Sign, Overflow, Negative, Zero, Carry
The Status Register
The Status Register (SREG) is central to the operation of every AVR instruction, because it contains the flags, and the global interrupt enable bit.
The behaviour of some instructions is affected by the state of one or more
flags
(e.g. Breq ‘branch if equal to zero’ inspects the ‘Z’ flag).
The behaviour of some instructions changes the state of one or more flags
(e.g. Dec will set the ‘Z’ flag if the new register value is zero.
The ‘I’ bit determines if an interrupt handler will be triggered when the
interrupt signal occurs.
Flags
Half-carry, Sign, Overflow, Negative, Zero, Carry
Global
Interrupt
enable 19
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

20. Effectively it forms a 9th bit (or 17th bit).
The Flags: Carry (C)
Generally, the Carry flag is set when an operation results in a value too large for the register size in use (i.e. a carry occurs).
Effectively it forms a 9th bit (or 17th bit).
Example – set Carry flag:
Ldi R16, 0xFF
Ldi R17, 0x01
Add R16, R17 0xFF + 0x01 = 0x100 → sets Carry flag
Example – test Carry flag:
Brcs label Will branch if Carry flag set, otherwise continue 20
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

21. Example – set Zero flag: Ldi R18, 0xF0 Ldi R19, 0x0F
The Flags: Zero (Z)
The Zero flag is set when an operation results in the value 0 being placed in the destination register.
Example – set Zero flag:
Ldi R18, 0xF0
Ldi R19, 0x0F
And R18, R19 0xF0 AND 0x0F = 0x00 → sets Zero flag Or
Ldi R20,5
Ldi R21,5
Cp R20,R Compare two registers which hold the same value
Example – test Zero flag:
Breq label Will branch if Zero flag set, otherwise continue 21
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

22. The Flags: Negative (N)
The Negative flag is set when an operation results in a negative value being placed in the destination register.
Example – set Negative flag:
Ldi R20, 0x60
Ldi R21, 0x70
Sub R20, R21 0x60 - 0x70 = - 0x10 → sets Negative flag
Example – test Negative flag:
Brmi label Will branch if Negative flag set, otherwise continue 22
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

23. The Flags: Two’s Complement Overflow (V) Part 1
The Overflow flag supports ‘Two’s Complement’ arithmetic operations.
Two's complement is computed by inverting all bits and adding ‘1’.
(In ‘signed’ notation negative numbers are represented using bit 7 as ‘sign bit’)
Generating negative numbers using two’s complement:
(decimal 0) becomes (decimal 0)
(decimal 1) becomes (decimal -1)
(decimal 2) becomes (decimal -2)
(decimal 127) becomes (decimal -127)
(decimal 128) becomes
(dec -0, but intended meaning is -128)
The absolute value of the most -ve no. (|−128| = 128) is too large to represent, so Overflow occurs. 23
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

24. The Flags: Two’s Complement Overflow (V) Part 2
Example – set Overflow flag:
Ldi R17, 0x80
Neg R x80 = - 0x80 → sets Overflow flag
(Neg performs 2s complement)
Some operations clear the Overflow flag regardless of result, e.g.
Or R16, R18 Clears Overflow flag
Example – test Overflow flag:
Brvs label Will branch if Overflow flag set, otherwise continue 24
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

25. The Flags: Sign (S) Part 1
The Sign flag is computed as N V (i.e. N exclusive OR V)
The sign bit is set if EITHER ONE of the Negative or Overflow flags is set, But NOT when both are set.
Example #1 – set / clear Sign flag:
Ldi R20, 0b (unsigned dec 132, signed dec -124)
Ldi R21, 0b (unsigned dec 2, signed dec 2)
Add R20, R21
Result is 0b (unsigned dec 134, signed dec -122)
(positive + positive = positive, or negative + positive = negative)
SETS Negative flag, CLEARS Overflow flag, SETS Sign flag + 25
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

26. The Flags: Sign (S) Part 2 Example #2 – set / clear Sign flag:
Ldi R22, 0b (unsigned dec 64, signed dec 64)
Ldi R23, 0b (unsigned dec 64, signed dec 64)
Add R22, R23 (unsigned dec 128, signed dec -128)
(positive + positive = positive, or positive + positive = negative)
SETS Negative flag, SETS Overflow flag, CLEARS Sign flag
Example – test Sign flag:
Brlt label (less than) Branch if Sign flag set, otherwise continue
Note there are different branches which you choose depending whether you want to interpret values as unsigned or signed:
Brlt (assumes signed interpretation) will branch if Sign flag set
Brlo (assumes unsigned interpretation) ignores Sign flag
Brge (assumes signed interpretation) branch if Sign flag cleared
Brsh (assumes unsigned interpretation) ignores Sign flag 26
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

27. The Flags: Half-carry (H)
The Half-carry flag is set when an operation results in a carry from the lower nibble to the higher nibble of the destination register.
Example – set/ clear Half-carry flag:
Ldi R16, 0b
Ldi R17, 0b
Add R16, R17 0x0A+ 0x06 = 0x10 → sets Half-carry flag
Ldi R16, 0b
Ldi R17, 0b
Add R16, R17 0x4A+ 0x24 = 0x6E → clears Half-carry flag
Example – test Half-carry flag:
Brhs label Will branch if Half-carry flag set, otherwise continue 27
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

28. The Stack pointer (introductory) 1
Use The main use of the Stack Pointer is to store the return address when a subroutine is called, so that once the subroutine completes, instruction execution can carry on from where it left off.
Initialisation The stack pointer is initialized to point to the highest address in SRAM, this is defined as RAMEND in the microcontroller-specific include file.
Operation When a subroutine call takes place (Call) the stack pointer places the 2-byte return address on the stack, and is decremented twice to point at the next location.
This process is reversed when a return from subroutine occurs (Ret); the stack pointer is incremented twice, retrieving the address to jump back to. 28
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich

29. The Stack pointer (introductory) 2 Effects on register contents
Call Subroutine STACK ← PC + 2
SP ← SP-2
PC ← Subroutine address
(i.e. jump to subroutine)
Ret SP ← SP+2
PC ← STACK
Stack operation is designed so subroutine calls can be nested
SP →
RAMEND
SRAM
Empty
No subroutine in use Subroutine #1 called Subroutine #2 called
Sub #1 ret addr
Sub #2 ret addr
Call Subroutine #1
Return from
subroutine
Call Subroutine #2 29
Embedded Systems Programming II Richard Anthony, Computer Science, The University of Greenwich