1. implementation of a 42 ps tdc based on fpga target
Speaker : Timothé Turko
Contributors : * Mcf. Foudil Dadouche
* Pr. Wilfried Uhring
* Dr. Imane Malass
* Jérémy Bartringer
* Mcf. Jean-Pierre Le Normand
2016 ICube

2. summary Context Time to Digital Converter Architecture
Methodology and realization
Encountered problems and solutions
Fast Time to Digital Converter characterization

3. context
“High-throughput time-correlated single photon counting in microfluidic droplets for enzymatic activity assays”
Why Fluorescence Lifetime (FL) measurements instead of Fluorescence Intensity measurements?
Due to the intrinsic character of FL studies, there are no interferences arising from volume differences, concentration, sample geometry or laser power, leading to high system sensitivity, accuracy and low noise level (Poisson noise).

4. context Time to Digital Converter (TDC) specification :
FPGA target (Cyclone IV)
Temporal resolution lower than 100 ps

5. definition Time to Digital Converter Electronic instrumentation
Signal processing
Time to Digital Converter
Absolute time
Digital (Binary)
Output
Events recognition providing a digital representation of the time

6. Tm = TFine1 + TCoarse – TFine2
how does it works ?
Two « Fine » counters
One « Coarse » counter
Tm = TFine1 + TCoarse – TFine2

7. architecture Tapped Delay Line Ringed Oscillator
Maximum resolution : 10 ps
Maximum resolution : 10 ps
The resolution is imposed by the FPGA’s technological limits and not by the TDC’s architecture

8. methodology and realization
One fine counter and associated control logic
One coarse counter and associated control logic
One Encoder to convert the TDC results on 8 bits
A data communication tool : USB

9. Logical simplification
first approach
Logical simplification !
It is necessary to constrain the logical elements placement

10. implemented solution New objectives:
Avoid the software data path simplification
Increase TDC resolution by reducing the propagation time through delay elements
Automate the elementary cells set-up process to optimize the design time and make possible the development of generic and adaptable structures
This method is focused on two main areas:
Using adders as delay elements and utilization
of the Carry Chain Logic of the FPGA
Using the Chip Planner tool

11. carry chain
Positionning failure of logical elements Achieve a minimum propagation delay
Spacial constrain of logical elements positions is mandatory

12. tdc characterization Using a delay generator: Start Stop
FPGA
Delay
Generator
The measurement last a long time
Allows to measure the jitter
Stop
Start signal  Delay generator trigger
Stop signal  Start signal delayed

13. tdc characterization Resolution : 42 ps Jitter : 90 ps RMS
INL : 132 ps RMS
DNL : 50 ps RMS

14. Replacement of the FPGA’s native DC/DC converter by a less noisy one.
tdc characterization
Replacement of the FPGA’s native DC/DC converter by a less noisy one.
Resolution : 42 ps
Jitter : 26 ps RMS
INL : 22 ps RMS
DNL : 13 ps RMS

15. results : fine tdc Resolution : 42 ps Jitter : 26 ps RMS
INL : 22 ps RMS
DNL : 13 ps RMS
Dead Time : 20 ns

16. Light source + SPAD = Random events generator
tdc characterization
Using Poisson process events:
Light source + SPAD = Random events generator
Statistically each TDC bins should go through the same number of event
Photon
SPAD
STOP
FPGA
START
Can not measure the Jitter
Start and Stop signals are not dependent. The delay between both of them is totally random
Very fast and accurate measurement

17. tdc characterization

18. tdc characterization Where : T is the total time range
M is the number of bins in the time range T

19. transfer function correction

20. case study Before correction After correction Visible static pattern
Lifetime : 4.21 ns ± 0.08 ns
Static pattern clearly attenuated
Lifetime : 4.19 ns ± 0.02 ns

21. Conclusion Reached resolution : 42 ps Jitter lower than 1 LSB
Fast and accurate characterization
Possibility to correct the transfer function