1. nan FIP The project April 24 2012 Eva. Gousiou BE/CO-HT
& the nanoFIP team
nan FIP

2. Outline
Introduction
Functionalities
Development tools
Integration

3. MicroFIP at CERN
WorldFIP: deterministic fieldbus used at CERN's LHC for several control systems.
Each system has a different use of MicroFIP: speeds, messages, macrocycles, variable size etc.
In total more than WorldFIP MicroFIPs installed in the LHC tunnel.
Control Room
WorldFIP master
WorldFIP slave
Signal Conditioner
Signal Conditioner
Signal Conditioner
LHC tunnel

4. nanoFIP application Setup
FieldTR
FieldDrive
FieldTR
FieldDrive
Master
fieldbus

5. nanoFIP application Setup
FieldTR
FieldDrive
FieldTR
FieldDrive
Master
Cons
fieldbus

6. nanoFIP application Setup
FieldTR
FieldDrive
FieldTR
FieldDrive
Master
Cons
fieldbus

7. nanoFIP application Setup
FieldTR
FieldDrive
Prod
FieldTR
FieldDrive
Master
fieldbus

8. nanoFIP Functionalities & Features
WorldFIP services:
Consumption of one addressed variable (up to 124 bytes)
Consumption of one broadcast variable (up to 124 bytes)
Production of one addressed variable (2, 8, 16,..,124 bytes)
appl
WorldFIP
Master
nFIP
consumption
production

9. nanoFIP Functionalities & Features
WorldFIP services:
Consumption of one addressed variable (up to 124 bytes)
Consumption of one broadcast variable (up to 124 bytes)
Production of one addressed variable (2, 8, 16,..,124 bytes)
appl
WorldFIP
Master
nFIP
consumption
production
Simple interface with the user:
Data transfer over an integrated memory or
application
WISHBONE
MEMORY
nanoFIP

10. nanoFIP Functionalities & Features
WorldFIP services:
Consumption of one addressed variable (up to 124 bytes)
Consumption of one broadcast variable (up to 124 bytes)
Production of one addressed variable (2, 8, 16,..,124 bytes)
appl
WorldFIP
Master
nFIP
consumption
production
Simple interface with the user:
Data transfer over an integrated memory or
application
WISHBONE
MEMORY
nanoFIP
Data transfer in stand-alone mode (2 bytes data exchange, no need for memory access).
16 bit DATA BUS

11. nanoFIP Functionalities & Features
WorldFIP services:
Consumption of one addressed variable (up to 124 bytes)
Consumption of one broadcast variable (up to 124 bytes)
Production of one addressed variable (2, 8, 16,..,124 bytes)
user
WorldFIP
Master
nFIP
consumption
production
Simple interface with the user:
Data transfer over an integrated memory or
application
WISHBONE
MEMORY
nanoFIP
Produced Var Ready!
Consumed Var. Ready!
ConsumedBR Var. Ready!
Data transfer in stand-alone mode (2 bytes data exchange, no need for memory access).
16 bit DATA BUS
Separate “data valid” outputs for each variable.

12. nanoFIP Functionalities & Features
WorldFIP services:
Consumption of one addressed variable (up to 124 bytes)
Consumption of one broadcast variable (up to 124 bytes)
Production of one addressed variable (2, 8, 16,..,124 bytes)
user
WorldFIP
Master
nFIP
consumption
production
Simple interface with the user:
Data transfer over an integrated memory or
application
WISHBONE
MEMORY
nanoFIP
Produced Var Ready!
Consumed Var. Ready!
ConsumedBR Var. Ready!
Data transfer in stand-alone mode (2 bytes data exchange, no need for memory access).
16 bit DATA BUS
Separate “data valid” outputs for each variable.
Features:
Communication in 3 speeds: 31.25kb/s, 1Mb/s, 2.5Mb/s.
Independent memories (124 bytes each) for consumed and produced data.
nanoFIP status byte available to the User and the Master.

13. Development tools Component v Synthesis v Mentor Graphics ModelSim v
Microsemi ProASIC3 A3P400 PQF208
No configuration loss
Reconfigurable
16 €/ unit
Synthesis v
Mentor Graphics Precision High-Reliability
Synopsys Synplify Premier
Xilinx ISE
Simulation v
Mentor Graphics ModelSim
Cadence
PaR v
Actel Designer, Actel Libero Environment

14. nanoFIP Integration v Applications
Use of the A3P400 PQF208 nanoFIP FPGA
Integration of the nanoFIP IP core into any ProASIC3 FPGA
Integration of the nanoFIP HDL into any FPGA; modification of proprietary memories
Applications
nanoFIPdiag
Stand-alone, chip
Radiation Monitoring
Memory 64 bytes, IP core

15. nanoFIP project report
Extras

16. Roadmap
2007 : Decision to in-source the WorldFIP technology
2008 : CERN purchases ALSTOM’s design information
2009 : Functional Specification defined
Q : Startup of HDL design and independent simulation bench
Q : Working hardware! Prototype board and software
Q : 20 test boards running continuously (billions of cycles)
Q : EMC tests (IEC )
Q : Two HDL reviews by 5 designer experts
Q : Code frozen
2012 : Support to the users’ developments

17. JTAG feature user user Master fieldbus FieldTR FieldDrive FieldTR

18. Testing nanoFIP VHDL code by Pablo and Eva
nanoFIP tested with independent Simulation Bench by Gonzalo
Functionality according to specs
User
simulation
Master
nanoFIP
Behavior under specs error conditions
Unspecified faulty conditions
nanoFIP Testing Board by an external company and Julien
Functionality according to specs
Limit operational conditions
Tests over time

19. Testing board development
The nanoFIP team
Erik, Project Manager
Julien, SW testing
Gonzalo, Simulations
Testing board development
Pablo, HW Engineer
Eva, HW Engineer

20. Outline
Introduction
Functionalities
Development tools
Integration