1. SPring-8 FADC Module
Compiled by Wen-Chen Chang
Updated: 07/12/2002

2. Requirement of TPC Electronics
Good energy resolution: measuring dE/dx from the charge readout of either wires or pads for the particle identification for K/p separation at low momentum.
Requirement of spatial resolution:
x,y < 300 m.
z < 1 mm.
Position information:
x(t),y(t): x from fired sense wires; y from interpolation of signals on pads(t).
z(t) from time bin of FADC time slice.
Timing information: fitting of pulse peak in FADC.
On-board zero-suppression to ensure fast data transfer and short system dead time.

3. Digitizer in TPC Electronic: FADC
Large data size:
High sampling rate: 40 MHz = 25 nsec.
Read-out bit (Nbit): 10 bits.
# of Time bins per event: ~600 time bins. (Max drift time/clock = 14 sec/25 nsec = 560 bins.)
1000 channels.
Trigger latency: 1 sec .
On-board zero-suppression.
Need of a large buffer size to store 4-5 events on board for one single VME readout.(16*600*5=48K per channel, w/o a zero suppression factor.)
High channel density.

4. SPring-8 FADC Module
Use TEXONO FADC and IHEP BES version as the starting point.
40 MHz; 10-bit FADC: ADC input 0-2 V range.
Shift register inside FPGA: max length = 100 time bin.
On-board FPGA for threshold suppression.
Buffer FIFO: dual port memory.
CPLD: controlling VME actions.
Free clock running.
VME 9U; 32 channels/module; 8 attached cards/module; 4 channel/card.

5. Main Electronic Components

6. SPring-8 FADC Module (4 channels, 10 bits, 40 MHz)
FIFO
FADC
OPA
FPGA

7. Mixed signal AD Converter Adapter Board
40 MHz sampling rate.
10 bits resolution with 2Vp-p dynamic range.
Clock distribution with Phase Lock Loop circuit.
On Board digital signal delay and
Real-Time ZERO-Suppression.
High capacity First In First Out Memory.
Easy to use with high density connector.

8. FADC Mother Board
Driver
CPLD
Clock Driver
VME Connector

9. 32 Channels, high sampling rate Flash AD converter.
VMEBus slave controller,
with high performance BLTransfer Mode.
FPGA,
digital signal control chip.
First In First Out memory.
Differential AD Converter (40 MHz)
16 channels differential signal input
connector.
32 Channels, high sampling rate
Flash AD converter.
Spring /03

10. Prototype 2

11. Prototype 2 : FADC card

12. Prototype 2: LED
Power
Download
Trigger
VME READ

13. Prototype 2: LEMO Input
Clock
Trigger
Reset
Busy

14. Prototype 2: Lab Test

15. Prototype 2: Lab test

16. Analog Input to ADC

17. 1-channel FPGA Block

18. FPGA Block

20. Data Format CS: Checksum bit Lowest Bit ND: Not defined. Header 116 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
* FADC Module number (6 bits) is set by two blue dip-switches on the lower part of VME 9U FADC.
Left one for the highest 2 bits and right one for the lowest 4 bits.
Header 1 CS 1 ND
*FADC Module Number (1-64)
Channel Number (1-32)
Header 2 CS 1 ND
Suppression Level (0-255)
Evt Num (1-8)
ADC CS 1 ND
ADC (0-1024)
Time CS 1 ND
Time (0-1024)
Trailer CS 1 ND
Number of ADC data bins (0-1024)

21. CSR Format Lowest Bit VME address: 0x01000016 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
Reset: counters, FIFO, BUSY. 1
Number of Events stored in FIFO before issuing IRQ 1
Num of Evts (0-31)

22. FADC VME Action List (A24/D16)
0x0i0000: CSR address to write; bit 9 for resetting FIFO and clear busy, bit 1-4, 10 for setting IRQ event numbers (Address modifier: 0x3D).
0x0i0100: address to read the all-merged 32 FIFOs’ content in BLT mode for FADC i. (Address modifier: 0x3B, 0x3F). Check up the last 16 bits of package after each read. If value = 0xFFFF, end of FIFO is reached and BLT read should be stopped.
0x0i0100+j*0x02: address to read the single FIFO content in AO mode for channel j. (Address modifier: 0x3D)
(channel 0, 0x0i0100, channel 1, 0x0i0102 ,….
channel 31, 0x0i013C, channel 32, 0x0i013E)
0x0i0100+j*0x02: address to write for setting the zero-suppression threshold for channel j. (Address modifier: 0x3D)
i: module number for VME address definition set by the dip-switch
on the upper right side of each VME 9U board.

23. CPLD FADC Trigger Clock 100MHz
The Control Flow of FADC
For each channel
DAQ Start
Trigger , Conversion
Master
Yes
NIM
< 5 events
Preamplifier Module
VME
CPU No
Trigger Count *Veto
Send IRQ to VME CPU
Trigger signal
DAQ READ FIFO
CPLD FADC Trigger Clock 100MHz
FADC Module
DAQ send Reset
Trigger
Clock
FADC clear BUSY
FADC
Reset
Clear trigger Veto
BUSY
Slave

24. Observation Window of Signals
Shift Register Length ( max 100*25ns = 2.5 s)
Trigger
Conversion Strobe
Sampling Counts ( max 1024*25ns=25s)

25. DAQ Test Trigger Logic SPring-8 32-channel FADC TEXONO MAMP LeCroy222
LTDS1
Rst
LTD0
Strb
SCLK
HTD0
Evnt
H VT
L VT
LeCroy222
START OR
BLANK
STOP
NIM
DEL
TTL
BUSY
1.0 10
100
LATCH
Full scale width
FBSY
INT
READ
CLK
Busy
Reset
+5V
+12V
-12V
-5.2V
SPring-8 32-channel FADC
Trigger
Voltage Reference
Clock Generator

26. TEXONO Online Event Display (400 KHz sine wave)

27. TEXONO Online Event Display (1 MHz sine wave)

28. ROOT Offline Event Display for 2 SPring-8 FADC (64 channels)
Module 1
Module 2

29. Events
02/09/2001: Prof. Imai and Ahn visited AS. Collaborating plan was discussed and finalized.
03/31/2001: Wen-Chen and Henry visited IHEP, Beijing and explored the R&D plan in IHEP.
05/31/2001: IHEP was not able to perform the R&D plan.
08/01/2001: Da-Shun visited IHEP for 3 weeks to learn the conceptual design.
02/01/2002: Prototype 1 boards made.
02/28/2002: Wen-Chen and Da-Shun tested prototype-1 boards with TPC at SPring-8.
04/25/2002: Finished up 64 channels of prototype-1 and deliver them to SPring-8.

30. Events
06/03/2002: Issue out prototype-2 (quasi-final) fabrication and SMT order.
06/24/2002: Deliver prototype-2 (64 channels) to SPring-8.
06/25/2002: System test with a complete electronic chain (Pre-amp, shaper, and FADC) with TPC at SPring-8.
07/02/2002: ordering of CPLD, PROM and other inexpensive components.
07/06/2002: Successful reading and decoding of pulser data by VME SPARC and UNIDAQ.
07/10/2002: Return prototype-2 (64 channels) to Taipei for fixing up the pedestals.

31. Plan to be finished:
07/25/2002: Return prototype-2 (64 channels) to SPring-8 for testing with TPC and Solenoid magnet.
08/15/2002: Finalize design and issue out the final production fabrication order (1440 channels).
09/01/2002: Send production boards for stuffing.
09/08/2002 – 09/25/2002: Test production boards in Taipei.
09/25/2002 – 10/15/2002: Delivery of production board, installation, system test and DAQ.
10/15/2002: Commission run with photon beams.