Chapter 1 Number Systems and Codes

Chapter 1 Number Systems and Codes

Number Systems (1) Positional Notation
N = (an-1an a1a0 . a-1a a-m)r (1.1) where . = radix point r = radix or base n = number of integer digits to the left of the radix point m = number of fractional digits to the right of the radix point an-1 = most significant digit (MSD) a-m = least significant digit (LSD) Polynomial Notation (Series Representation) N = an-1 x rn-1 + an-2 x rn a0 x r0 + a-1 x r a-m x r-m = (1.2) N = (251.41)10 = 2 x x x x x 10-2 Chapter 1 2 2

Number Systems (2) Binary numbers Digits = {0, 1}
( )2 = 1 x x x x x x x 2-2 = (26.75)10 1 K (kilo) = 210 = 1,024, 1M (mega) = 220 = 1,048,576, 1G (giga) = 230 = 1,073,741,824 Octal numbers Digits = {0, 1, 2, 3, 4, 5, 6, 7} (127.4)8 = 1 x x x x 8-1 = (87.5)10 Hexadecimal numbers Digits = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F} (B65F)16 = 11 x x x x 160 = (46,687)10 Chapter 1 3

Number Systems (3) Important Number Systems (Table 1.1) Chapter 1 4

Arithmetic (1) Binary Arithmetic Addition 111011 Carries 101011 Augend
Addend Subtraction Borrows Minuend Subtrahend Chapter 1 5

Arithmetic (2) Multiplication Division 1 1 0 1 0 Multiplicand
x Multiplier Product Chapter 1 6

Arithmetic (3) Octal Arithmetic (Use Table 1.4) Addition 1 1 1 Carries
Augend Addend Sum Subtraction Borrows Minuend Subtrahend Difference Chapter 1 7

Arithmetic (4) Multiplication Division 326 Multiplicand
x Multiplier 2732 Partial products 2404 Product Chapter 1 8

Arithmetic (5) Hexadecimal Arithmetic (Use Table 1.5) Addition
Carries 5 B A 9 Augend + D Addend 1 2 C 0 1 Sum Subtraction 9 10 A 10 Borrows A 5 B 9 Minuend D Subtrahend 4 D A C Difference Series Substitution Method Expanded form of polynomial representation: N = an-1rn-1 + … + a0r0 + a-1r-1 + … + a-mr-m (1.3) Conversion Procedure (base A to base B) Represent the number in base A in the format of Eq. 1.3. Evaluate the series using base B arithmetic. Examples: (11010)2  ( ? )10 (627)8  ( ? )10 ( )2  ( ? )8 (2AD.42)16  ( ? )10 Chapter 1 9

Arithmetic (6) Multiplication Division B9A5 Multiplicand
x D50 Multiplier 3A0390 Partial products 96D61 9A Product Chapter 1 10

Base Conversion (1) Series Substitution Method
Expanded form of polynomial representation: N = an-1rn-1 + … + a0r0 + a-1r-1 + … + a-mr-m (1.3) Conversation Procedure (base A to base B) Represent the number in base A in the format of Eq. 1.3. Evaluate the series using base B arithmetic. Examples: (11010)2 ( ? )10 N = 10 = (16)10 + (8) (2)10 + 0 = (26)10 (627)8  ( ? )10 N = 6 = (384)10 + (16)10 + (7)10 = (407)10 Chapter 1 11

Base Conversion (2) Radix Divide Method
Used to convert the integer in base A to the equivalent base B integer. Underlying theory: (NI)A = bn-1Bn-1 + … + b0B0 (1.4) Here, bi’s represents the digits of (NI)B in base A. NI bn-1Bn-1 + … + b1B1 + b0B0 ) / B = (Quotient Q1: bn-1Bn-2 + … + b1B0 ) + (Remainder R0: b0) In general, (bi)A is the remainder Ri when Qi is divided by (B)A. Conversion Procedure 1. Divide (NI)B by (B)A, producing Q1 and R0. R0 is the least significant digit, d0, of the result. 2. Compute di, for i = 1 … n - 1, by dividing Qi by (B)A, producing Qi+1 and Ri, which represents di. 3. Stop when Qi+1 = 0. Chapter 1 12

Base Conversion (3) Examples (315)10 = (473)8 (315)10 = (13B)16
Chapter 1 13

Base Conversion (4) Radix Multiply Method Used to convert fractions.
Underlying theory: (NF)A = b-1B-1 + b-2B-2 + … + b-mB-m (1.5) Here, (NF)A is a fraction in base A and bi’s are the digits of (NF)B in base A. B NF = B (b-1B-1 + b-2B-2 + … + b-mB-m ) = (Integer I-1: b-1) + (Fraction F-2: b-2B-1 + … + b-mB-(m-1)) In general, (bi)A is the integer part I-i, of the product of F-(i+1) (BA). Conversion Procedure 1. Let F-1 = (NF)A. 2. Compute digits (b-i)A, for i = 1 … m, by multiplying Fi by (B)A, producing integer I-i, which represents (b-i)A, and fraction F-(i+1). 3. Convert each digits (b-i)A to base B. Chapter 1 14

Base Conversion (5) Examples (0.479)10 = (0.3651…)8
MSD 0.479  8 6.656 0.832  8 5.248 0.656  8 LSD 0.248  8 … (0.479)10 = (0.0111…)2 MSD 0.479  2   2   2 LSD   2 Chapter 1 15

Base Conversion (6) General Conversion Algorithm Algorithm 1.1
To convert a number N from base A to base B, use (a) the series substitution method with base B arithmetic, or (b) the radix divide or multiply method with base A arithmetic. Algorithm 1.2 (a) the series substitution method with base 10 arithmetic to convert N from base A to base 10, and (b) the radix divide or multiply method with decimal arithmetic to convert N from base 10 to base B. Algorithm 1.2 is longer, but easier and less error prone. Chapter 1 16

Base Conversion (7) Example (18.6)9 = ( ? )11
(a) Convert to base 10 using series substitution method: N10 = 1    9-1 = … = (17.666…)10 (b) Convert from base 10 to base 11 using radix divide and multiply method: 7.326 0.666  11 3.586 0.326  11 6.446 0.586  11 N11 = ( …)11 Chapter 1 17

Base Conversion (8) When B = Ak Algorithm 1.3
(a) To convert a number N from base A to base B when B = Ak and k is a positive integer, group the digits of N in groups of k digits in both directions from the radix point and then replace each group with the equivalent digit in base B (b) To convert a number N from base B to base A when B = Ak and k is a positive integer, replace each base B digit in N with the equivalent k digits in base A. Examples ( )2 = (127.4)8 (group bits by 3) ( )2 = (B65F)16 (group bits by 4) Chapter 1 18

Signed Number Representation
Signed Magnitude Method N =  (an a0.a a-m)r is represented as N = (san a0.a a-m)rsm, (1.6) where s = 0 if N is positive and s = r -1 otherwise. N = -(15)10 In binary: N = -(15)10 = -(1111)2 = (1, 1111)2sm In decimal: N = -(15)10 = (9, 15)10sm Complementary Number Systems Radix complements (r's complements) [N]r = rn - (N)r (1.7) where n is the number of digits in (N)r. Positive full scale: rn-1 - 1 Negative full scale: -rn - 1 Diminished radix complements (r-1’s complements) [N]r-1 = rn - (N)r - 1 Chapter 1 19

Radix Complement Number Systems (1)
Two's complement of (N)2 = (101001)2 [N]2 = 26 - (101001)2 = ( )2 - (101001)2 = (010111)2 (N)2 + [N]2 = (101001)2 + (010111)2 = ( )2 If we discard the carry, (N)2 + [N]2 = 0. Hence, [N]2 can be used to represent -(N)2. [ [N]2 ]2 = [(010111)2]2 = ( )2 - (010111)2 = (101001)2 = (N)2. Two's complement of (N)2 = (1010)2 for n = 6 [N]2 = ( )2 - (1010)2 = (110110)2. Ten's complement of (N)10 = (72092)10 [N]10 = (100000)10 - (72092)10 = (27908)10. Chapter 1 20

Algorithm 1.4 Find [N]r given (N)r . Copy the digits of N, beginning with the LSD and proceeding toward the MSD until the first nonzero digit, ai, has been reached Replace ai with r - ai . Replace each remaining digit aj , of N by (r - 1) - aj until the MSD has been replaced. Example: 10's complement of (56700)10 is (43300)10 Example: 2's complement of (10100)2 is (01100)2. Example: 2’s complement of N = (10110)2 for n = 8. Put three zeros in the MSB position and apply algorithm 1.4 N = [N]2 = ( )2 The same rule applies to the case when N contains a radix point. Chapter 1 21

Algorithm 1.5 Find [N]r given (N)r . First replace each digit, ak , of (N)r by (r - 1) - ak and then add 1 to the resultant. For binary numbers (r = 2), complement each digit and add 1 to the result. Example: Find 2’s complement of N = ( )2 . N = Complement the bits +1 Add 1 [N]2 = ( )10 Example: Find 10’s complement of N = (40960)10 N = 40960 Complement the bits [N]2 = (59040)10 Chapter 1 22

Two's complement number system (See Table 1.6): Positive number : N = +(an-2, ..., a0)2 = (0, an-2, ..., a0)2cns, where Negative number: N = (an-1, an-2, ..., a0)2 -N = [an-1, an-2, ..., a0]2 (two's complement of N), Example: Two's complement number system representation of  (N)2 when (N)2 = ( )2 for n = 8: +(N)2 = (0, )2cns -(N)2 = [+(N)2]2 = [0, ]2 = (1, )2cns Chapter 1 23

Example: Two's complement number system representation of -(18)10 , n = 8: +(18)10 = (0, )2cns -(18)10 = [0, ]2 = (1, )2cns Example: Decimal representation of N = (1, )2cns N = (1, )2cns = -[1, ]2 = -(0, )2cns = -(24)2 . Chapter 1 24

Radix Complement Arithmetic (1)
Radix complement number systems are used to convert subtraction to addition, which reduces hardware requirements (only adders are needed). A - B = A + (-B) (add r’s complement of B to A) Range of numbers in two’s complement number system: , where n is the number of bits. 2n-1 -1 = (0, )2cns and -2n-1 = (1, )2cns If the result of an operation falls outside the range, an overflow condition is said to occur and the result is not valid. Consider three cases: A = B + C, A = B - C, A = - B - C, (where B  and C .) Chapter 1 25

Case 1: A = B + C (A)2 = (B)2 + (C)2 If A > 2n-1 -1 (overflow), it is detected by the nth bit, which is set to 1. Example: (7)10 + (4)10 = ? using 5-bit two’s complement arithmetic. + (7)10 = +(0111)2 = (0, 0111)2cns + (4)10 = +(0100)2 = (0, 0100)2cns (0, 0111)2cns + (0, 0100)2cns = (0, 1011)2cns = +(1011)2 = +(11)10 No overflow. Example: (9)10 + (8)10 = ? + (9)10 = +(1001)2 = (0, 1001)2cns + (8)10 = +(1000)2 = (0, 1000)2cns (0, 1001)2cns + (0, 1000)2cns = (1, 0001)2cns (overflow) Chapter 1 26

Case 2: A = B - C A = (B)2 + (-(C)2) = (B)2 + [C]2 = (B)2 + 2n - (C)2 = 2n + (B - C)2 If B  C, then A  2n and the carry is discarded. So, (A)2 = (B)2 + [C]|carry discarded If B < C, then A = 2n - (C - B)2 = [C - B]2 or A = -(C - B)2 (no carry in this case). No overflow for Case 2. Example: (14)10 - (9)10 = ? Perform (14)10 + (-(9)10) (14)10 = +(1110)2 = (0, 1110)2cns -(9)10 = -(1001)2 = (1, 0111)2cns (14)10 - (9)10 = (0, 1110)2cns + (1, 0111)2cns = (0, 0101)2cns + carry = +(0101)2 = +(5)10 Chapter 1 27

Example: (9)10 - (14)10 = ? Perform (9)10 + (-(14)10) (9)10 = +(1001)2 = (0, 1001)2cns -(14)10 = -(1110)2 = (1, 0010)2cns (9)10 - (14)10 = (0, 1001)2cns + (1, 0010)2cns = (1, 1011)2cns = -(0101)2 = -(5)10 Example: (0, 0100)2cns - (1, 0110)2cns = ? Perform (0, 0100)2cns + (- (1, 0110)2cns) - (1, 0110)2cns = two’s complement of (1,0110)2cns = (0, 1010)2cns (0, 0100)2cns - (1, 0110)2cns = (0, 0100)2cns + (0, 1010)2cns = (0, 1110)2cns = +(1110)2 = +(14)10 +(4)10 - (-(10)10) = +(14)10 Chapter 1 28

Case 3: A = -B - C A = [B]2 + [C]2 = 2n - (B)2 + 2n - (C)2 = 2n + 2n - (B + C)2 = 2n + [B + C]2 The carry bit (2n) is discarded. An overflow can occur, in which case the sign bit is 0. Example: -(7)10 - (8)10 = ? Perform (-(7)10) + (-(8)10) -(7)10 = -(0111)2 = (1, 1001)2cns , -(8)10 = -(1000)2 = (1, 1000)2cns -(7)10 - (8)10 = (1, 1001)2cns + (1, 1000)2cns = (1, 0001)2cns + carry = -(1111)2 = -(15)10 Example: -(12)10 - (5)10 = ? Perform (-(12)10) + (-(5)10) -(12)10 = -(1100)2 = (1, 0100)2cns , -(5)10 = -(0101)2 = (1, 1011)2cns -(7)10 - (8)10 = (1, 0100)2cns + (1, 1011)2cns = (0, 1111)2cns + carry Overflow, because the sign bit is 0. Chapter 1 29

Example: A = (25)10 and B = -(46)10 A = +(25)10 = (0, )2cns , -A = (1, )2cns B = -(46)10 = -(0, )2 = (1, )2cns , -B = (0, )2cns A + B = (0, )2cns + (1, )2cns = (1, )2cns = -(21)10 A - B = A + (-B) = (0, )2cns + (0, )2cns = (0, )2cns = +(71)10 B - A = B + (-A) = (1, )2cns + (1, )2cns = (1, )2cns + carry = -(0, )2cns = -(71)10 -A - B = (-A) + (-B) = (1, )2cns + (0, )2cns = (0, )2cns + carry = +(21)10 Note: Carry bit is discarded. Chapter 1 30

Summary When numbers are represented using two’s complement number system: Addition: Add two numbers. Subtraction: Add two’s complement of the subtrahend to the minuend. Carry bit is discarded, and overflow is detected as shown above. Radix complement arithmetic can be used for any radix. Chapter 1 31

Diminished Radix Complement Number systems (1)
Diminished radix complement [N]r-1 of a number (N)r is: [N]r-1 = rn - (N)r (1.10) One’s complement (r = 2): [N]2-1 = 2n - (N) (1.11) Example: One’s complement of ( )2 [N]2-1 = 28 - ( )2 - 1 = ( )2 - ( )2 - ( )2 = ( )2 - ( )2 = ( )2 Chapter 1 32

Diminished Radix Complement Number systems (2)
Example: Nine’s complement of (40960) [N]2-1 = (40960)10 - 1 = (100000)10 - (40960)10 - (00001)10 = (59040)10 - (00001)10 = (59039)10 Algorithm 1.6 Find [N]r-1 given (N)r . Replace each digit ai of (N)r by r a. Note that when r = 2, this simplifies to complementing each individual bit of (N)r . Radix complement and diminished radix complement of a number (N): [N]r = [N]r (1.12) Chapter 1 33

Diminished Radix Complement Arithmetic (1)
Operands are represented using diminished radix complement number system. The carry, if any, is added to the result (end-around carry). Example: Add +(1001)2 and -(0100)2 . One’s complement of +(1001) = 01001 One’s complement of -(0100) = 11011 = (carry) Add the carry to the result: correct result is Example: Add +(1001)2 and -(1111)2 . One’s complement of -(1111) = 10000 = (no carry, so this is the correct result). Chapter 1 34

Diminished Radix Complement Arithmetic (2)
Example: Add -(1001)2 and -(0011)2 . One’s complement of the operands are: and 11100 = (carry) Correct result is = Example: Add +(75)10 and -(21)10 . Nine’s complements of the operands are: 075 and 978 = 1053 (carry) Correct result is = 054 Example: Add +(21)10 and -(75)10 . Nine’s complements of the operands are: 021 and 924 = 945 (no carry, so this is the correct result). Chapter 1 35

Computer Codes (1) Code is a systematic use of a given set of symbols for representing information. Example: Traffic light (Red: stop, Yellow: caution, Blue: go). Numeric Codes To represent numbers. Fixed-point and floating-point number. Fixed-point Numbers Used for signed integers or integer fractions. Sign magnitude, two’s complement, or one’s complement systems are used. Integer: (Sign bit) + (Magnitude) + (Implied radix point) Fraction: (Sign bit) + (Implied radix point) + (Magnitude) Chapter 1 36

Computer Codes (2) Excess or Biased Representation
An excess-K representation of a code C: Add K to each code word C. Frequently used for the exponents of floating-point numbers. Excess-8 representation of 4-bit two’s complement code: Table 1.8 Chapter 1 37

Floating Point Numbers (1)
N = M  rE, where (1.13) M (mantissa or significand) is a significant digits of N E (exponent or characteristic) is an integer exponent. In general, N =  (an a0 .a a-m)r is represented by N =  (.an a-m)r  rn M is usually represented in sign magnitude: M = (SM.an a-m)rsm , where (1.14) (.an a-m)r represents the magnitude SM = (0: positive, 1: negative) (1.15) Chapter 1 38

E is usually coded in excess-K two’s complement. K is called a bias and usually selected to be 2e-1 (e is the number of bits). So, biased E is: -2e-1   Excess-K form of E is written as: E = (be-1, be b0)excess-K (1.16) where be-1 is the sign bit. Combining Eqs. (1.14) and (1.16), we have N = (SMbe-1be b0an a-m)r (1.17) representing N = (1.18) The number 0 is represented by an all-zero word. Chapter 1 39

Multiple representations of a given number: N = M rE (1.19) = (M r)  rE (1.20) = (M  r)  rE (1.21) Example: M = +( )2 M = +( )2 = ( )2  (1.22) = ( )2 25 (1.23) = ( )2 26 (1.24) … Normalization is used for a unique representation: mantissa has a nonzero value in its MSD position. Eq gives the normalization representation of M. Chapter 1 40

Floating-point Number Formats Typical single-precision format Typical extended-precision format Chapter 1 41

Example: N = ( )2, where n + m = 10 and e = 5. Assume that a normalized sign magnitude fraction is used for M and that Excess-16 two’s complement is used for E. N = ( )2 = ( )2  26 M = +( )2 = ( )2sm E = +(6)10 = +(0110)2 = (00110)2cns Add the bias 16 = (10000)2 to E E = = 10110 So, E = (1, 0110)excess-16 Combining M and E, we have N = (0, 1, 0110, )fp Chapter 1 42

Characters and Other Codes (1)
To represent information as strings of alpha-numeric characters. Binary Coded Decimal (BCD) Used to represent the decimal digits 4 bits are used. Each bit position has a weight associated with it (weighted code). Weights are: 8, 4, 2, and 1 from MSB to LSB (called code). BCD Codes: 0: : : : : 0100 5: : : : : 1001 Used to encode numbers for output to numerical displays Used in processors that perform decimal arithmetic. Example: (9750)10 = ( )BCD Chapter 1 43

ASCII (American Standard Code for Information Interchange) Most widely used character code. See Table 1.11 for 7-bit ASCII code. The eighth bit is often used for error detection (parity bit) Example: ASCII code representation of the word Digital Character Binary Code Hexadecimal Code D i g t a l C Chapter 1 44

Gray Code Cyclic code: A circular shifting of a code word produces another code word. Gray code: A cyclic code with the property that two consecutive code words differ in only 1 bit (the distance between the two code words is 1). Gray code for decimal numbers : See Table 1.12 Chapter 1 45

Error Detection Codes and Correction Codes(1)
An error: An incorrect value in one or more bits. Single error: An incorrect value in only one bit. Multiple error: One or more bits are incorrect. Errors are introduced by hardware failures, external interference (noise), or other unwanted events. Error detection/correction code: Information is encoded in such a way that a particular class of errors can be detected and/or corrected. Let I and J be n-bit binary information words w(I): the number of 1’s in I (weight) d(I, J): the number of bit positions in which I and J differ (distance) Example: I = ( ) and J = ( ) w(I) = 4 and w(J) = 3 d(I, J) = 3. Chapter 1 46

General Properties Minimum distance, dmin, of a code C: for any two code words I and J in C, d(I, J) dmin A code provides t error correction plus detection of s additional errors if and only if the following inequality is satisfied. 2t + s + 1  dmin (1.25) Example: Single-error detection (SED): s = 1, t = 0, dmin = 2. Single-error correction (SEC): s = 0, t = 1, dmin = 3. Single-error correction and double-error detection (SEC and DED): s = t = 1, dmin = 4. Chapter 1 47

Relationship between the minimum distance between code words and the ability to detect and correct errors: Chapter 1 48

Simple Parity Code Concatenate (|) a parity bit, P, to each code word of C. Odd-parity code: w(P|C) is odd. Even-parity code: w(P|C) is even. Parity coding on magnetic tape: Chapter 1 49

Example: Odd-parity code for ASCII code characters: Error detection: Check whether a code word has the correct parity. Single-error detection code (dmin = 2). Two-out-of-Five Code Each code word has exactly two 1’s and three 0’s. Detects single errors and multiple errors in adjacent bits. Chapter 1 50

Hamming Codes (1) Multiple check bits are employed.
Each check bit is defined over (or covers) a subset of the information bits. Subsets overlap so that each information bit is in at least two subsets. dmin is equal to the weight of the minimum-weight nonzero code word. Hamming Code 1 (Table 1.14) dmin = 3, single error correction code. Let the set of all code words: C an error word with single error: ce the correct code word for the error word: c then, d(ce,c) = 1 and d(ce, w) > 1 for all other w  C (see Table 1.15) So, a single error can be detected and corrected by finding out the code word which differs in 1 bit position from the error word. Chapter 1 51

Hamming Codes (2) A code word consists of 4 information bits and 3 check bits: c = (i3 i2 i1 i0 c2 c1 c0) Each check bit covers: c2: i3, i2, i1 c1: i3, i2, i0 c0: i3, i1, i0 This relationship is specified by the generating matrix, G: (1.26) Encoding of an information word i to produce a code word, c: c = iG (1.27) Chapter 1 52

Hamming Codes (3) Decoding can be done using the parity-check matrix, H: (1.28) H matrix is can be derived from G matrix. An n-tuple c is a code word generated by G if and only if HcT = 0 (1.29) Let d be a data word corresponding to a code word c, which has been corrupted by an error pattern e. Then d = c + e (1.30) Decoding: Compute the syndrome, s, of d using H matrix. s tells the position of the erroneous bit. Chapter 1 53

Hamming Codes (4) Computation of the syndrome: s = HdT (1.31)
= H(c + e)T = HcT + HeT = 0 + HeT = HeT (1.32) Note: All computations are performed using modulo-2 arithmetic. See Table 1.16 for the syndromes and error patterns. Chapter 1 54

Hamming Codes (5) Hamming Code 2 (Table 1.14)
dmin = 4, single error correction and double-error detection. The generator and parity-check matrices are: (1.33) (1.34) Odd-weight-column code: H matrix has an odd number of ones in each column. Example: Hamming Code 2. Has many properties; single-error correction, double-error detection, multiple-error detection, low cost encoding and decoding, etc. Chapter 1 55

Hamming Codes (6) Hamming codes are most easily designed by specifying the H matrix. For any positive integer m  3, there exists an (n, k) SEC Hamming code with the following properties: Code length: n = 2m - 1 Number of information bits: k = 2m - m - 1 Number of check bits: n - k = m Minimum distance: dmin = 3 The H matrix is an n m matrix with all nonzero m-tuples as its column. A possible H matrix for a (15, 11) Hamming code, when m = 4: (1.35) Chapter 1 56

Hamming Codes (7) Example: A Hamming code for encoding five (k = 5) information bits. Four check bits are required (m = 4). So, n = 9. A (9, 5) code can be obtained by deleting six columns from the (15,11) code shown above. The H and G matrices are: (1.36) (1.37) Chapter 1 57

Chapter 2 Algebraic Methods for the Analysis and Synthesis of Logic Circuits
58

Fundamentals of Boolean Algebra (1)
Basic Postulates Postulate 1 (Definition): A Boolean algebra is a closed algebraic system containing a set K of two or more elements and the two operators  and +. Postulate 2 (Existence of 1 and 0 element): (a) a + 0 = a (identity for +), (b) a 1 = a (identity for ) Postulate 3 (Commutativity): (a) a + b = b + a, (b) a b = b a Postulate 4 (Associativity): (a) a + (b + c) = (a + b) + c (b) a (bc) = (ab) c Postulate 5 (Distributivity): (a) a + (bc) = (a + b) (a + c) (b) a (b + c) = ab + ac Postulate 6 (Existence of complement): (a) (b) Normally is omitted. Chapter 2 59

Fundamental Theorems of Boolean Algebra Theorem 1 (Idempotency): (a) a + a = a (b) aa = a Theorem 2 (Null element): (a) a + 1 = 1 (b) a0 = 0 Theorem 3 (Involution) Properties of 0 and 1 elements (Table 2.1): OR AND Complement a + 0 = 0 a0 = 0 0' = 1 a + 1 = 1 a1 = a 1' = 0 Chapter 2 60

Theorem 4 (Absorption) (a) a + ab = a (b) a(a + b) = a Examples: (X + Y) + (X + Y)Z = X + Y [T4(a)] AB'(AB' + B'C) = AB' [T4(b)] Theorem 5 (a) a + a'b = a + b (b) a(a' + b) = ab B + AB'C'D = B + AC'D [T5(a)] (X + Y)((X + Y)' + Z) = (X + Y)Z [T5(b)] Chapter 2 61

Theorem 6 (a) ab + ab' = a (b) (a + b)(a + b') = a Examples: ABC + AB'C = AC [T6(a)] (W' + X' + Y' + Z')(W' + X' + Y' + Z)(W' + X' + Y + Z')(W' + X' + Y + Z) = (W' + X' + Y')(W' + X' + Y + Z')(W' + X' + Y + Z) [T6(b)] = (W' + X' + Y')(W' + X' + Y) [T6(b)] = (W' + X') [T6(b)] Chapter 2 62

Theorem 7 (a) ab + ab'c = ab + ac (b) (a + b)(a + b' + c) = (a + b)(a + c) Examples: wy' + wx'y + wxyz + wxz' = wy' + wx'y + wxy + wxz' [T7(a)] = wy' + wy + wxz' [T7(a)] = w + wxz' [T7(a)] = w [T7(a)] (x'y' + z)(w + x'y' + z') = (x'y' + z)(w + x'y') [T7(b)] Chapter 2 63

Theorem 8 (DeMorgan's Theorem) (a) (a + b)' = a'b' (b) (ab)' = a' + b' Generalized DeMorgan's Theorem (a) (a + b + … z)' = a'b' … z' (b) (ab … z)' = a' + b' + … z' Examples: (a + bc)' = (a + (bc))' = a'(bc)' [T8(a)] = a'(b' + c') [T8(b)] = a'b' + a'c' [P5(b)] Note: (a + bc)' a'b' + c' Chapter 2 64

More Examples for DeMorgan's Theorem (a(b + z(x + a')))' = a' + (b + z(x + a'))' [T8(b)] = a' + b' (z(x + a'))' [T8(a)] = a' + b' (z' + (x + a')') [T8(b)] = a' + b' (z' + x'(a')') [T8(a)] = a' + b' (z' + x'a) [T3] = a' + b' (z' + x') [T5(a)] (a(b + c) + a'b)' = (ab + ac + a'b)' [P5(b)] = (b + ac)' [T6(a)] = b'(ac)' [T8(a)] = b'(a' + c') [T8(b)] Chapter 2 65

Theorem 9 (Consensus) (a) ab + a'c + bc = ab + a'c (b) (a + b)(a' + c)(b + c) = (a + b)(a' + c) Examples: AB + A'CD + BCD = AB + A'CD [T9(a)] (a + b')(a' + c)(b' + c) = (a + b')(a' + c) [T9(b)] ABC + A'D + B'D + CD = ABC + (A' + B')D + CD [P5(b)] = ABC + (AB)'D + CD [T8(b)] = ABC + (AB)'D [T9(a)] = ABC + (A' + B')D [T8(b)] = ABC + A'D + B'D [P5(b)] Chapter 2 66

Switching Functions Switching algebra: Boolean algebra with the set of elements K = {0, 1} If there are n variables, we can define switching functions. Sixteen functions of two variables (Table 2.3): A switching function can be represented by a table as above, or by a switching expression as follows: f0(A,B)= 0, f6(A,B) = AB' + A'B, f11(A,B) = AB + A'B + A'B' = A' + B, ... Value of a function can be obtained by plugging in the values of all variables: The value of f6 when A = 1 and B = 0 is: = = 1. Chapter 2 67

Truth Tables (1) Shows the value of a function for all possible input combinations. Truth tables for OR, AND, and NOT (Table 2.4): Chapter 2 68

Truth Tables (2) Truth tables for f(A,B,C) = AB + A'C + AC' (Table 2.5) Chapter 2 69

Algebraic Forms of Switching Functions (1)
Literal: A variable, complemented or uncomplemented. Product term: A literal or literals ANDed together. Sum term: A literal or literals ORed together. SOP (Sum of Products): ORing product terms f(A, B, C) = ABC + A'C + B'C POS (Product of Sums) ANDing sum terms f (A, B, C) = (A' + B' + C')(A + C')(B + C') Chapter 2 70

A minterm is a product term in which all the variables appear exactly once either complemented or uncomplemented. Canonical Sum of Products (canonical SOP): Represented as a sum of minterms only. Example: f1(A,B,C) = A'BC' + ABC' + A'BC + ABC (2.1) Minterms of three variables: Chapter 2 71

Compact form of canonical SOP form: f1(A,B,C) = m2 + m3 + m6 + m7 (2.2) A further simplified form: f1(A,B,C) =  m (2,3,6,7) (minterm list form) (2.3) The order of variables in the functional notation is important. Deriving truth table of f1(A,B,C) from minterm list: Chapter 2 72

Example: Given f(A,B,Q,Z) = A'B'Q'Z' + A'B'Q'Z + A'BQZ' + A'BQZ, express f(A,B,Q,Z) and f '(A,B,Q,Z) in minterm list form. f(A,B,Q,Z) = A'B'Q'Z' + A'B'Q'Z + A'BQZ' + A'BQZ = m0 + m1 + m6 + m7 =  m(0, 1, 6, 7) f '(A,B,Q,Z) = m2 + m3 + m4 + m5 + m8 + m9 + m10 + m11 + m12 + m13 + m14 + m15 =  m(2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15) (2.6) AB + (AB)' = 1 and AB + A' + B' = 1, but AB + A'B'  1. Chapter 2 73

A maxterm is a sum term in which all the variables appear exactly once either complemented or uncomplemented. Canonical Product of Sums (canonical POS): Represented as a product of maxterms only. Example: f2(A,B,C) = (A+B+C)(A+B+C')(A'+B+C)(A'+B+C') (2.7) Maxterms of three variables: Chapter 2 74

f2(A,B,C) = M0M1M4M5 (2.8) = M(0,1,4,5) (maxterm list form) (2.9) The truth table for f2(A,B,C): Chapter 2 75

Truth tables of f1(A,B,C) of Eq. (2.3) and f2(A,B,C) of Eq. (2.7) are identical. Hence, f1(A,B,C) =  m (2,3,6,7) = f2(A,B,C) = M(0,1,4,5) (2.10) Example: Given f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C'), construct the truth table and express in both maxterm and minterm form. f(A,B,C) = M1M3M5M7 = M(1,3,5,7) =  m (0,2,4,6) Chapter 2 76

Relationship between minterm mi and maxterm Mi: For f(A,B,C), (m1)' = (A'B'C)' = A + B + C' = M1 In general, (mi)' = Mi (2.11) (Mi)' = ((mi)')' = mi (2.12) Chapter 2 77

Example: Relationship between the maxterms for a function and its complement. For f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C') The truth table is: Chapter 2 78

From the truth table f '(A,B,C) = M(0,2,4,6) and f(A,B,C) = M(1,3,5,7) Since f(A,B,C) f '(A,B,C) = 0, (M0M2M4M6)(M1M3M5M7) = 0 or In general, (2.13) Another observation from the truth table: f(A,B,C) =  m (0,2,4,6) = M(1,3,5,7) f '(A,B,C) =  m (1,3,5,7) = M(0,2,4,6) Chapter 2 79

Derivation of Canonical Forms (1)
Derive canonical POS or SOP using switching algebra. Theorem 10. Shannon's expansion theorem (a). f(x1, x2, …, xn) = x1 f(1, x2, …, xn) + (x1)' f(0, x2, …, xn) (b). f(x1, x2, …, xn) = [x1 + f(0, x2, …, xn)] [(x1)' + f(1, x2, …, xn)] Example: f(A,B,C) = AB + AC' + A'C f(A,B,C) = AB + AC' + A'C = A f(1,B,C) + A' f(0,B,C) = A(1B + 1C' + 1'C) + A'(0B + 0C' + 0'C) = A(B + C') + A'C f(A,B,C) = A(B + C') + A'C = B[A(1+C') + A'C] + B'[A(0 + C') + A'C] = B[A + A'C] + B'[AC' + A'C] = AB + A'BC + AB'C' + A'B'C f(A,B,C) = AB + A'BC + AB'C' + A'B'C = C[AB + A'B1 + AB'1' + A'B'1] + C'[AB + A'B0 + AB'0' + A'B'0] = ABC + A'BC + A'B'C + ABC' + AB'C' Chapter 2 80

Derivation of Canonical Forms (2)
Alternative: Use Theorem 6 to add missing literals. Example: f(A,B,C) = AB + AC' + A'C to canonical SOP form. AB = ABC' + ABC = m6 + m7 AC' = AB'C' + ABC' = m4 + m6 A'C = A'B'C + A'BC = m1 + m3 Therefore, f(A,B,C) = (m6 + m7) + (m4 + m6) + (m1 + m3) = m(1, 3, 4, 6, 7) Example: f(A,B,C) = A(A + C') to canonical POS form. A = (A+B')(A+B) = (A+B'+C')(A+B'+C)(A+B+C')(A+B+C) = M3M2M1M0 (A+C')= (A+B'+C')(A+B+C') = M3M1 f(A,B,C) = (M3M2M1M0)(M3M1) = M(0, 1, 2, 3) Chapter 2 81

Incompletely Specified Functions
A switching function may be incompletely specified. Some minterms are omitted, which are called don't-care minterms. Don't cares arise in two ways: Certain input combinations never occur. Output is required to be 1 or 0 only for certain combinations. Don't care minterms: di Don't care maxterms: Di Example: f(A,B,C) has minterms m0, m3, and m7 and don't-cares d4 and d5. Minterm list is: f(A,B,C) = m(0,3,7) + d(4,5) Maxterm list is: f(A,B,C) = M(1,2,6)·D(4,5) f '(A,B,C) = m(1,2,6) + d(4,5) = M(0,3,7)·D(4,5) f (A,B,C)= A'B'C' + A'BC + ABC + d(AB'C' + AB'C) = B'C' + BC (use d4 and omit d5) Chapter 2 82

Electronic Logic Gates (1)
Electrical Signals and Logic Values A signal that is set to logic 1 is said to be asserted, active, or true. An active-high signal is asserted when it is high (positive logic). An active-low signal is asserted when it is low (negative logic). Chapter 2 83

Chapter 2 84

Chapter 2 85

Chapter 2 86

Chapter 2 87

Basic Functional Components (1)
AND (a) AND logic function. (b) Electronic AND gate. (c) Standard symbol. (d) IEEE block symbol. Chapter 2 88

OR (a) OR logic function. (b) Electronic OR gate. (c) Standard symbol. (d) IEEE block symbol. Chapter 2 89

Meaning of the designation  1 in IEEE symbol: Chapter 2 90

NOT (a) NOT logic function. (b) Electronic NOT gate. (c) Standard symbol. (d) IEEE block symbol. Chapter 2 91

Positive Versus Negative Logic Chapter 2 92

AND Gate Usage in Negative Logic (a) AND gate truth table (L = 1, H = 0) (b) Alternate AND gate symbol (in negative logic) (c) Preferred usage (d) Improper usage y = a·b = (2.14) (2.15) Chapter 2 93

OR Gate Usage in Negative Logic (a) OR gate truth table(L = 1, H = 0) (b) Alternate OR gate symbol (in negative logic) (c) Preferred usage (d) Improper usage (2.16) (2.17) Chapter 2 94

Example 2.32: Building smoke alarm system Components: two smoke detectors, a sprinkler, and an automatic telephone dialer Behavior: Sprinkler is activated if either smoke detector detects smoke. When both smoke detector detect smoke, fire department is called. Signals: : Active-low outputs from two smoke detectors. : Active-low input to the sprinkler : Active-low input to the telephone dialer. Logic equations (2.18) (2.19) Chapter 2 95

Logic diagram of the smoke alarm system Chapter 2 96

NAND (a) NAND logic function (b) Electronic NAND gate (c) Standard symbol (d) IEEE block symbol Chapter 2 97

Matching signal polarity to NAND gate inputs/outputs (a) Preferred usage (b) Improper usage Additional properties of NAND gate: Hence, NAND gate may be used to implement all three elementary operators. Chapter 2 98

AND, OR, and NOT gates constructed exclusively from NAND gates Chapter 2 99

NOR (a) NAND logic function (b) Electronic NAND gate (c) Standard symbol (d) IEEE block symbol Chapter 2 100

Matching signal polarity to NOR gate inputs/outputs (a) Preferred usage (b) Improper usage Additional properties of NAND gate: Hence, NAND gate may be used to implement all three elementary operators. Chapter 2 101

AND, OR, and NOT gates constructed exclusively from NOR gates. Chapter 2 102

Exclusive-OR (XOR) fXOR(a, b) = a  b = (2.24) (a) XOR logic function (b) Electronic XOR gate (c) Standard symbol (d) IEEE block symbol Chapter 2 103

POS of XOR a  b [P2(a), P6(b)] [P5(b)] Some other useful relationships a  a = (2.25) a  = (2.26) a  0 = a (2.27) a  1 = (2.28) (2.29) a  b = b  a (2.30) a  (b  c) = (a  b)  c (2.31) Chapter 2 104

Output of XOR gate is asserted when the mathematical sum of inputs is one: The output of XOR is the modulo-2 sum of its inputs. Chapter 2 105

Exclusive-NOR (XNOR) fXNOR(a, b) = a b (2.32) (a) XNOR logic function (b) Electronic XNOR gate (c) Standard symbol (d) IEEE block symbol Chapter 2 106

SOP and POS of XNOR a b [P2] [T8(a)] [T8(b)] [P5(b)] [P6(b), P2(a)] = a b Chapter 2 107

Analysis of Combinational Circuits (1)
Digital Circuit Design: Word description of a function  a set of switching equations  hardware realization (gates, programmable logic devices, etc.) Digital Circuit Analysis: Hardware realization  switching expressions, truth tables, timing diagrams, etc. Analysis is used To determine the behavior of the circuit To verify the correctness of the circuit To assist in converting the circuit to a different form. Chapter 2 108

Algebraic Method: Use switching algebra to derive a desired form. Example 2.33: Find a simplified switching expressions and logic network for the following logic circuit (Fig. 2.21a). Chapter 2 109

Write switching expression for each gate output: The output is: Simplify the output function using switching algebra: [Eq. 2.24] [T8] [T5(b)] [T4(a)] = b c [Eq. 2.32] Therefore, f (a,b,c) = (b c)' = Chapter 2 110

Example 2.34: Find a simplified switching expressions and logic network for the following logic circuit (Fig. 2.22). Chapter 2 111

Derive the output expression: f(a,b,c) = = [T8(b)] = [T8(a)] = [Eq. 2.24] = [P5(b)] = [P6(b), T4(a)] = [T4(a)] = [T9(a)] = [T7(a)] Chapter 2 112

Truth Table Method: Derive the truth table one gate at a time. The truth table for Example 2.34: Chapter 2 113

Analysis of Timing Diagrams Timing diagram is a graphical representation of input and output signal relationships over the time dimension. Timing diagrams may show intermediate signals and propagation delays. Chapter 2 114

Example 2.35: Derivation of truth table from a timing diagram Chapter 2 115

Propagation Delay Physical characteristics of a logic circuit to be considered: Propagation delays Gate fan-in and fan-out restrictions Power consumption Size and weight Propagation delay: The delay between the time of an input change and the corresponding output change. Typical two propagation delay parameters: tPLH = propagation delay time, low-to-high-level output tPHL = propagation delay time, high-to-low-level output Approximation: Chapter 2 116

Propagation delay through a logic gate Chapter 2 117

Power dissipation and propagation delays for several logic families (Table 2.7) Chapter 2 118

Propagation delays of primitive 74LS series gates (Table 2.8) Chapter 2 119

Example 2.36: Given a circuit diagram and the timing diagram, find the truth table and minimum switching expression. Chapter 2 120

Synthesis of Combinational Logic Circuits (1)
AND-OR and NAND Networks Switching expression must be in SOP form. Example: [T3] [T8(a)] where and Chapter 2 121

OR-AND and NOR Networks Switching expression must be in POS form. Example: [T3] [T8(b)] where and Chapter 2 122

Two-level Circuits Input signals pass through two levels of gates before reaching the output. Implementation procedure for NAND (NOR) logic: Step 1. Express the function in minterm (maxterm) list form. Step 2. Write out the minterms (maxterms) in algebraic form. Step 3. Simplify the function in SOP (POS) form. Step 4. Transform the expression into the NAND (NOR) form. Step 5. Draw the NAND (NOR) logic diagram. Chapter 2 123

Circuits with more than two levels are often needed due to fan-in constraints. Chapter 2 124

Example 2.37: NAND implementation of f (X,Y,Z) = m(0,3,4,5,7) 1. f (X,Y,Z) = m(0,3,4,5,7) 2. f (X,Y,Z) = m0 + m3 + m4 + m5 + m7 [T6(a)] 4a. [T4] or 4b. [T3] [T8(a)] Chapter 2 125

AND-OR-invert Circuits A set of AND gates followed by a NOR gate. Used to readily realize two-level SOP circuits. 7454 circuit: Chapter 2 126

Factoring A technique to obtain higher-level forms of switching functions. Higher-level forms: May need less hardware May be used when there are fan-in constraints More difficult to design Slower Example 2.39: Chapter 2 127

Example 2.40: f (a,b,c,d) = m(8,13) with only two-input AND and OR gates. Write the canonical SOP form: f (a,b,c,d) = m(8,13) = (2.34) Two four-input AND gates and one two-input OR gate are needed. Apply factoring: (2.35) Chapter 2 128

Example 2.41: A burglar alarm with four control switches, each of which produces logic 1 when: Switch A: Secret switch is closed Switch B: Safe is in its normal position in the closet Switch C: Clock is between 1000 and 1400 hours Switch D: Closet door is closed. Write the equations of the control logic that produces logic 1 when the safe is moved AND the secret switch is closed, OR the closet is opened after banking hours, the closet is opened with the control switch open. Chapter 2 129

Example 2.42: The Doe family voter: Vote for either hamburgers (0) or chicken (1). Majority wins. If Mom and Dad agree, they win. John (Dad): A, Jane (Mom):B, Joe: C, Sue: D. The logic function is: Chapter 2 130

Example 2.43: Logic equations for a circuit that adds two 2-bit binary numbers (A1A0)2 and (B1B0)2, and produces sum bits (S1S0)2 and carry bit C1; A1A0 + B1B0 C1S1S0 Chapter 2 131

Truth Table: A1 A0 B1 B0 C1 S1 S0 Logic equations: S0 = S1 = C1 = Chapter 2 132

Reduced equations: S0 = S1 = C1 = Chapter 2 133

Computer-aided Design (1)
Design Cycle Chapter 2 134

Digital Circuit Modeling Purpose of modeling: Helps the designer formalize a solution. To check errors, verify correctness, and predict timing characteristics. CAD tools are available for design optimization and transformation of design from abstract form to a physical realization. Model can represent different levels of design abstraction. Chapter 2 135

High-level abstract model (behavioral model) Describes only desired behavior. Usually represented using a hardware description language (HDL), e.g., VHDL or Verilog. Other representation mechanisms: logic equations, truth tables, and minterm or maxterm lists. Chapter 2 136

Behavioral models of a full-adder circuit: (a) block diagram, (b) truth table, (c) logic equations. Chapter 2 137

VHDL behavioral model of a full adder circuit (Figure 2.38) Entity defines the interface between the circuit and the outside world. Architecture defines the function implemented within the circuit. Multiple architectures may be defined for a given entity. Structural model Interconnection of components. Behavior is deduced from the behavioral models of individual components and their interconnection. Represented by: Logic or schematic diagram Netlist (textual representation of schematic diagram) HDL description of circuit structures. Chapter 2 138

Structural models of a full-adder circuit: (a) schematic diagram, (b) netlist In a netlist, each circuit element is defined as follows: gate_name, gate_type, output, input1, input2, …, inputN VHDL structural model of a full-adder circuit: Figure 2.40. Chapter 2 139

Mixed-mode model Contains both behavioral and structural components. Mixed-mode model of the full-adder circuit: (a) full-adder block diagram, (b) circuit for sum function, (c) truth table for carry function. Chapter 2 140

Design synthesis process Chapter 2 141

Capture tools Each circuit model in the design process must be captured in a format that can be stored and processed by a digital computer. Schematic capture: an interactive graphics tool with which a designer draws a logic diagram. Chapter 2 142

Schematic capture process Chapter 2 143

Logic Simulation Three primary purposes: 1. Logic verification: only logical correctness is checked. 2. Performance analysis: propagation delays and potential timing problems are analyzed. 3. Test development (fault simulation): helps develop optimal test set. Simulation environment Chapter 2 144

Simulation Test Inputs Test set: a carefully designed set of test inputs. For logic verification, a list of input vectors is used (time is ignored). For timing analysis, the time of each input change is also specified. functional test set for input tabular waveform full-adder waveform format format Chapter 2 145

Event-Driven Simulation Event: a change in the value of a signal at a given time. Event-driven simulation example for an AND gate: Chapter 2 146

Event-driven simulation procedure Input test set is converted into a set of events. The set of events are entered into an event queue (or event list). In each simulation step, the first event is retrieved and is made to occur. Output of each affected gate is recomputed, and new event is created. Record of all events along with output results are maintained. Simulation continues until the event queue is empty or time limit expires. Chapter 2 147

Debugging a full-adder using simulation erroneous simulation output: expanded simulation: full-adder error in s at time isolates error to n3 circuit Chapter 2 148

Detection of static hazard via simulation A glitch in g at time t3 can be detected from the output waveforms. This occurs because both e and f become 0 momentarily between t2 and t3. Chapter 2 149

Symbolic Logic Signal Values Designers sometimes need signal values other than just 0 or 1. Logic signal values are represented by a state and a strength. A third state X represents an unknown state or a potential problem. Truth tables for three-valued logic (with X added) Signal strength values: Forcing (F): signal line is strongly forced to a given state. Resistive (R): signal line is weakly forced to a given state. Floating (Z): signal line is not forced forced at all. Unknown (U): signal strength cannot be determined. Chapter 2 150

Signal strengths are used to resolve conflicting gate outputs: output resolved in favor of output value stronger signal unable to be resolved Chapter 2 151

Primitive Device Delay Models Every primitive logic gate has an intrinsic delay. A gate can be modeled as an ideal (zero-delay) gate and a transport delay element. Different models of transport delays: Unit/Nominal Delay Rise Fall Delay Ambiguous or Min/Max Delay Chapter 2 152

Unit/Nominal Delay Unit delay: assign to each gate in a circuit the same unit delay. Nominal delay: delays are determined separately for each type of gate (e.g., on time unit for NOR and two time units for XOR). Chapter 2 153

Rise/Fall Delay Different delays for 0 to 1 transition and 1 to 0 transition. tPLH (rise time): propagation delay from low to high. tPHL (fall time): propagation delay from high to low. Chapter 2 154

Ambiguous or Min/Max Delay Sometimes it is impossible to predict exact rise or fall time of a signal. For worst-case performance analysis, {tmin, tmax} is specified for each timing parameter. Chapter 2 155

A problem with min/max delay: the results tend to be pessimistic. circuit model worst-case delays: ambiguity region gets larger at each successive level Chapter 2 156

Inertial Delay An input value must persist for some minimum duration of time to provide the output with the needed inertia to change. The minimum duration is called inertial delay. Effect of inertial delay: Gate model with both inertial delay and transport delay: Chapter 2 157

Chapter 3 Simplification of Switching Functions

Simplification Goals Goal -- minimize the cost of realizing a switching function Cost measures and other considerations Number of gates Number of levels Gate fan in and/or fan out Interconnection complexity Preventing hazards Two-level realizations Minimize the number of gates (terms in switching function) Minimize the fan in (literals in switching function)

Example 3.1 Determine the form and the number of terms and literals in each of the following. g(A,B,C) = AB + A B + AC Two-level form, three products , two sums, six literals. f(X,Y,Z) = X Y(Z + Y X) + Y Z Four-level form, four products, two sums, seven literals.

Minimization Methods Commonly used techniques Characteristics
Boolean algebra postulates and theorems Karnaugh maps Quine-McCluskey method Petrick’s method Generalized concensus algorithm Characteristics Heuristics (suboptimal) Algorithms (optimal)

Minimum SOP and POS Representations
The minimum sum of products (MSOP) of a function, f, is a SOP representation of f that contains the fewest number of product terms and fewest number of literals of any SOP representation of f. Example -- f(a,b,c,d) = m(3,7,11,12,13,14,15) = ab + acd + acd = ab + cd The minimum product of sums (MPOS) of a function, f, is a POS representation of f that contains the fewest number of sum terms and the fewest number of literals of any POS representation of f. Example -- f(a,b,c,d) = M(0,1,2,4,5,6,8,9,10) = (a + c)(a + d)(a + b + d)(b + c + d) = (a +c)(a + d)(b + c)(b + d)

Karnaugh Maps Karnaugh maps (K-maps) -- convenient tool for representing switching functions of up to six variables. K-maps form the basis of useful heuristics for finding MSOP and MPOS representations. An n-variable K-map has 2n cells with each cell corresponding to a row of an n-variable truth table. K-map cells are labeled with the corresponding truth-table row. K-map cells are arranged such that adjacent cells correspond to truth rows that differ in only one bit position (logical adjacency). Switching functions are mapped (or plotted) by placing the function’s value (0,1,d) in each cell of the map.

Figure 3.1 Venn diagram and equivalent K-map for two variables

Figure 3.2 Venn diagram and equivalent K-map for three variables

Figure 3.3 (a) -- (d) K-maps for four and five variables

Figure 3.3 (e) -- (f) K-maps for six variables

Plotting (Mapping) Functions in Canonical Form on a K-map
Let f be a switching function of n variables where n  6. Assume that the cells of the K-map are numbered from 0 to 2n where the numbers correspond to the rows of the truth table of f. If mi is a minterm of f, then place a 1 in cell i of the K-map. Example -- f(A,B,C) = m(0,3,5) If Mi is a maxterm of f, then place a 0 in cell i. Example -- f(A,B,C) = M(1,2,4,6,7) If di is a don’t care of f, then place a d in cell i.

Figure 3.4 Plotting functions on K-maps
f(A,B,C) = m(0,3,5) = M(1,2,4,6,7)

Figure 3. 5 K-maps for f(a,b,Q,G) in Example 3. 4 (a) Minterm form
Figure 3.5 K-maps for f(a,b,Q,G) in Example 3.4 (a) Minterm form. (b) Maxterm form. f(a,b,Q,G) = m(0,3,5,7,10,11,12,13,14,15) = M(1,2,4,6,8,9)

Figure 3.6 K-map of Figure 3.5(a) with variables reordered: f(Q,G,b,a).
f(Q,G,b,a) = m(0,12,6,14,9,13,3,7,11,15) = m(0,3,6,7,9,11,12,13,14,15)

Plotting Functions in Algebraic Form
Example f(A,B,C) = AB + BC Example f(A,B,C,D) = (A + C)(B + C)(B + C + D) Example f(A,B,C,D)= (A+B)(A+C+D)(B+C+D)

Figure 3.7 -- Example 3.6. (a) Venn diagram form. (b) Sum of minterms. (c) Maxterms.
f(A,B,C) = AB + BC

Figure 3.8 -- Example 3.7. (a) Maxterms, (b) Minterms, (c) Minterms of f .
f(A,B,C,D) = (A + C)(B + C)(B + C + D)

Figure 3.9 -- Example 3.8. (a) K-map of f, (b) K-map of f.
f(A,B,C,D)= (A+B)(A+C+D)(B+C+D)

Simplification of Switching Functions Using K-maps
K-map cells that are physically adjacent are also logically adjacent. Also, cells on an edge of a K-map are logically adjacent to cells on the opposite edge of the map. If two logically adjacent cells both contain logical 1s, the two cells can be combined to eliminate the variable that has value 1 in one cell’s label and value 0 in the other. This is equivalent to the algebraic operation, aP + aP =P where P is a product term not containing a or a. Example -- f(A,B,C,D) = m(1,2,4,6,9)

Figure 3.10 K-map for Example 3.9
f(A,B,C,D) = m(1,2,4,6,9)

Simplification Guidelines for K-maps
Each cell of an n-variable K-map has n logically adjacent cells. Cells may be combined in groups of 2,4,8,…,2k. A group of cells can be combined only if all cells in the group have the same value for some set of variables. Always combine as many cells in a group as possible. This will result in the fewest number of literals in the term that represents the group. Make as few groupings as possible to cover all minterms. This will result in the fewest product terms. Always begin with the “loneliest” cells.

Prime Implicants and Covers
An implicant is a product term that can cover minterms of a function. A prime implicant is a product term that is not covered by another implicant of the function. An essential prime implicant is a prime implicant that covers at least one minterm that is not covered by any other prime implicant. A set of implicants is said to be a cover of a function if each minterm of the function is covered by at least one implicant in the set. A minimal cover is a cover that contains the smallest number of prime implicants and the smallest number of literals..

Figure 3.11 K-map illustrating implicants
Minterms: {AB C, A BC, A BC, ABC, ABC} Groups of two minterms: {A B, AB, A C, BC, BC} Groups of four minterms: {B} Prime implicants: {A C, B} Cover = {A C, B} MSOP = A C + B

Algorithm 3.1 -- Generating and Selecting Prime Implicants
1. Count the number of adjacencies for each minterm on the K-map. 2. Select an uncovered minterm with the fewest number of adjacencies. Make an arbitrary choice if more than one choice is possible. 3. Generate a prime implicant for this minterm and put it in the cover. If this minterm is covered by more than one prime implicant, select the one that covers the most uncovered minterms. 4. Repeat steps 2 and 3 until all minterms have been covered.

Figure 3.12 -- Example 3.10 (Illustrating Algorithm 3.1)
f(A,B,C,D) = m(2,3,4,5,7,8,10,13,15)

Algorithm 3.2 -- Generating and Selecting Prime Implicants (Revisited)
1. Circle all prime implicants on the K-map. 2. Identify and select all essential prime implicants for the cover. 3. Select a minimum subset of the remaining prime implicants to complete the cover, that is, to cover those minterms not covered by the essential prime implicants.

Figure 3.13 -- Example 3.11 (Illustrates Algorithm 3.2)
f(A,B,C,D) = m(2,3,4,5,7,8,10,13,15)

Figure 3.14 -- Example 3.12 f(A,B,C,D) = m(0,5,7,8,10,12,14,15)

Figure 3.15 -- Example 3.13 f(A,B,C,D) = m(1,2,3,6) = AC + BC

Figure 3.16 -- Example 3.14 f(A,B,C,D) = BD + BC + BCD

Figure 3.17 -- Example 3.15 Function with no essential prime implicants.
f(A,B,C,D) = m(0,4,5,7,8,10,14,15)

Figure 3. 18 -- Example 3. 16 Minimizing a five-variable function
Figure Example 3.16 Minimizing a five-variable function. f(A,B,C,D,E) = m(0,2,4,7,10,12,13,18,23,26,28,29)

Prime Implicates and Covers
A implicate is a sum term that can cover maxterms of a function. A prime implicate is a sum term that is not covered by another implicate of the function. An essential prime implicate is a prime implicate that covers at least one maxterm that is not covered by any other prime implicate. A set of implicate is said to be a cover of a function if each maxterm of the function is covered by at least one implicate in the set. A minimal cover is a cover that contains the smallest number of prime implicate and the smallest number of literals..

Algorithm 3.3 -- Generating and Selecting Prime Implicates
1. Count the number of adjacencies for each maxterm on the K-map. 2. Select an uncovered maxterm with the fewest number of adjacencies. Make an arbitrary choice if more than one choice is possible. 3. Generate a prime implicate for this maxterm and put it in the cover. If this maxterm is covered by more than one prime implicate, select the one that covers the most uncovered maxterms. 4. Repeat steps 2 and 3 until all maxterms have been covered.

Algorithm 3.4 -- Generating and Selecting Prime Implicates (Revisited)
1. Circle all prime implicates on the K-map. 2. Identify and select all essential prime implicates for the cover. 3. Select a minimum subset of the remaining prime implicates to complete the cover, that is, to cover those maxterms not covered by the essential prime implicates.

Example 3.17 -- Find the minimum POS form of the function f(A,B,C,D) = M(0,1,2,3,6,9,14)
Figure K-maps for Example 3.17.

Algorithm 3.5 -- Finding MPOS of f from f
1. Plot the complement function f on the K-map. 2. Use algorithm 3.1 or 3.2 to produce a MSOP of f. 3. Complement f and use DeMorgan’s theorem to produce a MSOP of f.

Example Find the MPOS of the following function using Algorithm 3.5 f(A,B,C,D) = M(0,1,2,3,6,9,14) Figure K-map of f f = A B + B C D + BCD f = (A + B)(B + C + D )(B + C + D)

Example 3.19 -- Minimum covers of f(A,B,C,D) =  M (3,4,6,8,9,11,12,14) and its complement.
Figure 3.21

Figure 3.22 Finding a minimal POS expression for a 5-variable function.

Figure 3.23 Deriving POS and SOP forms of a function.

Figure 3.24 K-maps for Example 3.22.
Example Minimizing a Function with Don’t Cares. f(A,B,C,D) = m(1,3,4,7,11) + d(5,12,13,14,15) = M(0,2,6,8,9,10)  D(5,12,13,14,15) SOP POS Figure K-maps for Example 3.22.

Example 3.23 -- Design a circuit to distinguish BCD digits  5 from those  5.
Figure block diagram and truth table.

f(A,B,C,D) = (A + B)(A + C + D)
Example 3.23 (concluded) MSOP MPOS Figure Use of don’t cares for SOP and POS forms. f(A,B,C,D) = A + BD + BC; f(A,B,C,D) = (A + B)(A + C + D)

Timing Hazards in Combinational Logic Circuits
Hazards are undesirable changes in the output of a combinational logic circuit caused by unequal gate propagation delays. Static hazard (glitch) -- the output momentarily changes from the correct or static state Static 1 hazard -- the output changes from 1 to 0 and back to 1 Static 0 hazard -- the output changes from 0 to 1 and back to 0 Dynamic hazard (bounce) -- the output changes multiple times during a change of state Dynamic 0 to 1 hazard -- the output changes from 0 to 1 to 0 to 1 Dynamic 1 to 0 hazard -- the output changes from 1 to 0 to 1 to 0

Figure 3.27 (a)--(b) Illustration of a static hazard.

Figure 3.27 (c) Illustration of a static hazard (con’t)

Figure 3.27 (d) Illustration of a static hazard (con’t).

Figure 3.28 Identifying hazards on a K-map.

Figure 3.29 Hazard-free network.

Figure 3.30 (a)--(b) Example of a static-0 hazard.

Figure 3.30 (c)--(d) Example of a static-0 hazard (con’t).

Figure 3.31 Dynamic hazards.

Quine-McCluskey Minimization Method
Advantages over K-maps Can be computerized Can handle functions of more than six variables Overview of the method Given the minterms of a function Find all prime implicants (steps 1 and 2) Partition minterms into groups according to the number of 1’s Exhaustively search for prime implicants Find a minimum prime implicant cover (steps 3 and 4) Construct a prime implicant chart Select the minimum number of prime implicants

Example Use the Q-M method to find the MSOP of the function f(A,B,C,D) = m(2,4,6,8,9,10,12,13,15) Figure K-map for example 3.30.

Step 1 -- List Prime Implicants in Groups (Example 3.24)

Step 2 -- Generate Prime Implicants (Example 3.24)

Step 3 -- Prime Implicant Chart (Example 3.24)

Step 4 -- Reduced Prime Implicant Chart (Example 3.24)

The Resulting Minimal Realization of f
f(A,B,C,D) = PI1 + PI3 + PI4 + PI7 = = AC + B CD + A BD + ABD

How the Q-M Results Look on a K-map
Figure Grouping of terms.

Covering Procedure Step 1 -- Identify any minterms covered by only one PI. Select these PIs for the cover. Step 2 -- Remove rows covered by the PIs identified in step 1. Remove minterms covered by the removed rows. Step 3 -- If a cyclic chart results from step 2, go to step 5. Otherwise, apply the reduction procedure of steps 1 and 2. Step 4 -- If a cyclic chart results from step 3, go to step 5. Otherwise return to step 1. Step 5 -- Apply the cyclic chart procedure. Repeat step 5 until a void chart or noncyclic chart chart is produced. In the latter case, return to step 1.

Coverage Example f(A,B,C,D) = m(0,1,5,6,7,8,9,10,11,13,14,15)

Reduced PI Charts

Cyclic PI Charts 1. No essential PIs. 2. No row or column coverage.

Using the Q-M Procedure with Incompletely Specified Functions
1. Use minterms and don’t cares when generating prime implicants 2. Use only minterms when finding a minimal cover Example Find a minimal sum of products of the following function using the Quine-McCluskey procedure.

Minimizing Table for Example 3.25

PI Chart for Example 3.25

Results of Minimization for Example 3.25
f(A,B,C,D,E) = PI1 + PI4 + PI5 + PI6 + PI7 OR = PI2 + PI4 + PI5 + PI6 + PI7

Minimizing Circuits with Multiple Outputs

Minimizing Table for Example 3.26

Prime Implicant Chart for Example 3.26

Reduced Prime Implicant Chart for Example 3.26

Minimum Realizations for Example 3.26

Figure 3.34 Reduced multiple-output circuit.

Petrick’s Algorithm for Selecting a Minimal Cover (Algorithm 3.6)
1. Find all prime implicants of the function to be minimized. 2. Construct a prime implicant table and identify and remove all essential prime implicants and their corresponding rows and columns. 3. Write a POS function that contains a product term for each minterm left in the reduced prime implicant chart that includes a variable for each prime implicant that covers the minterm. 4. Convert the function to SOP form. 5. Select a minimal cover by finding a product term representing the fewest prime implicants and literals.

Example 3.27 -- Example of Petrick’s Algorithm

The Cover Function for Example 3.27
C = (PI2 + PI3)(PI4 + PI5)(PI2 + PI4)(PI3 + PI6) = PI2PI3 PI5 + PI3PI4 + PI2 PI4PI6 + PI2 PI5PI6 Minimal cover = {PI1*, PI7*, PI3, PI4}

Figure 3.35

Figure 3.36

Figure 3.37

Figure 3.38

Figure P3.1

Chapter 4 -- Modular Combinational Logic

Decoders

Decoder Realization

More complex decoders

Example 4.1 -- Realize f(Q,X,P) = m(0,1,4,6,7) = M(2,3,5)

Example 4.1 (concluded)

K-Channel multiplexing/demultiplexing
Figure 4.22

Four-to-one multiplexer design

Use a 74151A multiplexer to Realize f(x1,x2,x3) = m(0,2,3,5)
Figure 4.30

Half Adders Figure 4.35 (a) -- (c)

Full Adders Figure 4.35 (d) -- (g)

Ripple Carry Adder Figure 4.36

Addition Time for a Basic Ripple-Carry Adder
Let tgate = the propogation delay through a typical logic gate Half adder propagation delays tadd = 3 tgate tcarry = 2 tgate Full adder propagation delays Ripple-Carry Adder (n-bits) tadd = (n - 1)2 tgate + 3 tgate = (2n + 1) tgate

SN7482 Two-Bit Pseudo Parallel Adder Module
Package Pin Configuration

SN7482 Pseudo Parallel Adder -- Truth Table

SN7482 Pseudo Parallel Adder -- Logic Diagram

SN7482 Two-Bit Adder -- Logic Equations
C1 = C0A1 + C0B1 + A1B1 (4.20) 1 = C0C1 + A1C1 + B1C1 + A1B1C0 = C1(C0 + A1 + B1) + A1B1C0 = (C0+A1)(C0+B1)(A1+B1) (C0 +A1+B1) +A1B1C0 = (C0+ A1B1)(A1+B1)(C0 +A1+B1) +A1B1C0 (4.21) = [C0(A1+B1)+ C0A1B1](A1+B1)+A1B1C0 = C0A1B1+C0A1B1+C0A1B1+A1B1C0 = C0  A1  B1 Similarly C2 = C1A2 + C1B2 + A2B2 (4.22) 2 = C1  A2  B2

Add Time for SN7482 Adder Circuits
SN7482 propagation delays t1 = 5 tgate tC1 = 2 tgate t2 = 6 tgate tC2 = 4 tgate SN7482-based ripple-carry adder (n-bits) tadd = (2n + 2) tgate

SN7483 Four-Bit Adder Module
Package Pin Configuration

SN7483 Four-Bit Adder Module -- Logic Diagram

SN7483 Four-Bit Adder -- Logic Equations
Pi = (BiAi)(Ai + Bi) = (Ai + Bi)(Ai + Bi) = Ai  Bi (4.24) i = Pi  Ci-1 = Ai  Bi  Ci (4.25) C1 = [C0(A1B1) + (A1 + B1)] = [C0(A1B1)](A1 + B1) = (C0+(A1B1))(A1 + B1) = C0A1 + C0B1 + A1B (4.26) Similarly Ci = Ci-1Ai + Ci-1Bi + AiBi

Add Times for SN7483 Adder Circuits
SN7483 propagation delays t1 = 3 tgate t2 = t3 = t4 = 4 tgate tC1 = tC2 = tC3 = tC4 = 3 tgate SN7483-based Ripple-Carry Adder (n-bits) tadd = (3m + 1) tgate where m = n/4.

Fully Parallel Three-Bit Adder
c0 = x0y (4.30) s0 = x0  y0 c1 = x1y1c0’+x1y1c0+x1y1’c0+x1’y1c0 = x1y1+(x1y1)c0 = x1y1+(x1y1)(x0y0) (4.31) s1 = x1y1c0 = x1y1 x0y0 c2 = x2y2+(x2y2)c1 = x2y2+(x2y2)[x1y1+(x1y1)(x0y0)] = x2y2+(x2y2)(x1y1)+(x2y2)(x1y1)(x0y0) (4.32) s2 = x2y2c1 = x2y2[x1y1+(x1y1)(x0y0)]

Add Time for a Fully Parallel Adder
Assuming a three-level realization tadd = 3 tgate However, the fan in requirements become impractical as n increases.

Carry Look-Ahead Adders -- Basic Idea
Recall that ci = xiyi + xici-1 + yici-1 = xiyi + xiyici-1 + xiyici-1 + xiyici-1 + xi yici-1 = xiyi + xiyici-1 + xi yici-1 = xiyi + (xiyi + xi yi)ci-1 = xiyi + (xi  yi)ci-1 Let gi = xiyi [carry generate] (4.33) pi = xi  yi [carry propagate] (4.34) Then ci = gi + pi ci-1 si = pi  ci-1 (4.38)

Carry Look-Ahead Adders -- Three-Bit Example
c0 = g (4.35) s0 = p0 c1 = g1 + p1c0 = g1 + p1g (4.36) s1 = p1  c0 c2 = g2 + p2c1 = g2 + p2(g1 + p1g0) = g2 + p2g1 + p2p1g0 (4.37) s2 = p2  c1

Carry Look-Ahead Adder Design
Figure 4.39

Add Times for Carry Look-Ahead Adders
Adder modules tg = tp = ts = tgate CLA module tc = 2 tgate Overall tadd = tgate + 2 tgate + tgate = 4 tgate

Binary Subtraction Circuits
Recall that (R)2 = (P)2 - (Q)2 = (P)2 + (-Q)2 = (P)2 + [Q]2 = (P)2 + (Q)2 + 1 For an SN7483 adder ()2 = (A)2 + (B)2 + (C0)2 (4.39) where  = 4321, A = A4A3A2A1, and B = B4B3B2B1 If C0 = 0, A = P, and B = Q, then ()2 = (P)2 + (Q)2 . If C0 = 1, A = P, and B = Q, then ()2 = (P)2 - (Q)2 .

Two’s Complement Adder/Subtracter
Figure 4.41

Arithmetic Overflow Detection
an-1 bn-1 cn-2 cn-1 sn V

Overflow Detection Circuits
Figure 4.42

Decoders

Decoder Realization

More complex decoders

Example 4.1 -- Realize f(Q,X,P) = m(0,1,4,6,7) = M(2,3,5)

Example 4.1 (concluded)

K-Channel multiplexing/demultiplexing
Figure 4.22

Four-to-one multiplexer design

Use a 74151A multiplexer to Realize f(x1,x2,x3) = m(0,2,3,5)
Figure 4.30

Chapter 6 -- Introduction to Sequential Devices

The Sequential Circuit Model
Figure 6.1

State Tables and State Diagrams
Figure 6.2

Sequential Circuit Example
Figure 6.3

Latch and Flip-flop Timing
Figure 6.4

TTL Memory Elements

Set Latch Figure 6.5

Reset Latch Figure 6.6

Set-Reset Latch (SR latch)
Figure 6.7

NAND SR Latch Figure 6.8

Set-Reset Latch Timing Diagram
Figure 6.9

SR Latch Propagation Delays

SR Latch Characteristics
Figure 6.11 Q* = S + RQ

SN74279 Latch with Two Set Inputs
Figure 6.12

Gated SR Latch Figure 6.13

Gated SR Latch Characteristics
Figure 6.14 Q* = SC + RQ + C Q

Delay Latch (D latch) Figure 6.15

D Latch Characteristics
Figure 6.16 Q* = DC + CQ

D Latch Timing Diagram Figure 6.17

D Latch Timing Constraints
Figure 6.18

The SN74LS75 D Latch Figure 6.19

Propagation Delays and Time Constraints for the SN74LS75

Hazard-Free D Latch, the SN74116
Figure 6.20 Q* = DC + CQ + DC

Master-Slave SR Flip-flop
Figure 6.20

SR Master-Slave Flip-Flop Characteristics
Figure 6.22 Q* = S + RQ

Master-Slave D Flip-Flop
Figure 6.23

Master-Slave D Flip-Flop Characteristics
Figure 6.24 Q* = D

Pulse-Triggered JK Flip-Flop Characteristics
Figure 6.25 Q* = KQ + JQ

Pulse-Triggered JK Flip Realization
Figure 6.26

The SN7476 Dual Pulse-Triggered JK Flip-Flop
Figure 6.27

SN7474 Dual Positive-Edge-Triggered D Flip-Flop
Figure 6.28

SN7474 Excitation Table Figure 6.29

SN7474 Flip-Flop Timing Specifications
Figure 6.30

SN74175 Positive-Edge-Triggered D Flip-Flop
Figure 6.31 (a)

SN74273 Positive-Edge-Triggered D Flip-Flop
Figure 6.31 (b)

SN74LS73A Edge-Triggered JK Flip-Flop Logic Diagram
Figure 6.32 (a)

SN74LS73A Logic Symbols Figure 6.32 (b) and (c)

SN74276 and SN74111 Edge-Triggered JK Flip-Flops
Figure 6.32 (d) and (e)

Negative-Edge-Triggered T Flip-Flop
Figure 6.33

Edge-Triggered T Flip-Flop Characteristics
Figure 6.34 Q* = Q

Clocked T Flip-Flop Figure 6.35

Excitation Table for Clocked T Flip-Flops
Figure 6.36 Q* = TQ + TQ

The Clocked T Flip-Flop Timing Diagram
Figure 6.37

Summary of Latch and Flip-Flop Characteristics

SE555 Precision Timing Module
Figure 6.38

Astable Operation of The SE555
Figure 6.39

Monostable (One shot) Device Realization
Figure 6.40

PROM-based Sequential Circuits
Figure 6.41

PROM-based Sequential Circuit Example
Figure 6.41

Prime Number Sequencer
Figure 6.43

Chapter 7 -- Modular Sequential Logic

Serial-in, Serial-out Shift Register

Generic Shift Register

SN74164 Serial-in, Serial-out Shift Register

SN74164 Function Table and Package

SN74165 8-bit Serial-In, Serial-out Shift register

SN74165 Timing Diagram

Parallel Accumulator

Synchronous Binary Counter

SN74163 Synchronous Binary Counter

Asynchronous Down Counter

Synchronous Up/Down Counter

SN74160 Synchronous Decade Counter

SN74160 Logic Diagram

Asynchronous BCD Counter

Digital Timer Block Diagram
Figure 7.22

SN7492A Asynchronous Counter

SN7492A Timing Diagram

SN7492A State Diagrams

Modulo-N Asynchronous Counter

SN74293 Asynchronous Binary Counter

Modulo-13 Counter Design -- Example 7.1

Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits

The Synchronous Sequential Circuit Model
Figure 8.1

Mealy Machine Model Figure 8.2

Mealy Machine Timing Diagram -- Example 8.1
Figure 8.3

Moore Machine Model Figure 8.4

Moore Machine Timing Diagram -- Example 8.2
Figure 8.5

Analysis of Sequential Circuit State Diagrams -- Example 8.3
Figure 8.6

Timing Diagram for Example 8.3
Figure 8.7

Analysis of Sequential Circuit Logic Diagrams
Figure 8.8

Timing Diagram for Figure 8.8 (a)

State Table and State Diagram for Figure 8.8 (a)

K-Maps for Circuit of Figure 8.8 (a)

Synchronous Sequential Circuit with T Flip-Flop -- Example 8.4
Figure 8.12

Timing Diagram for Example 8.4
Figure 8.13

State Table and State Diagram for Example 8.4
Figure 8.14

K-Maps for Example 8.4 Figure 8.15

Synchronous Sequential Circuit with JK Flip-flops -- Example 8.5
Figure 8.16

Timing Diagram and State Table for Example 8.5
Figure 8.17

K-Maps for Example 8.5 Figure 8.18

Generating the State Table From K-maps -- Example 8.5
Figure 8.19

Synchronous Sequential Circuit Synthesis
Figure 8.20

Introductory Synthesis Example -- Example 8.6
Figure 8.21

Flip-flop Input Tables -- Example 8.6
Figure 8.22

Generating the JK Flip-flop Excitation Maps -- Example 8.7
Figure 8.23

Clocked JK Flip-Flop Implementation -- Example 8.7
Figure 8.24

Application Equation Method for Deriving Excitation Equations -- Example 8.8
Figure 8.25

Sequence Recognizer for 01 Sequence -- Example 8.9
Figure 8.26

Synthesis of the 01 Recognizer with SR Flip-flops
Figure 8.27

Realization of 01 Recognizer with T Flip-flops
Figure 8.28

Design of a Recognizer for the Sequence 1111 -- Example 8.11
Figure 8.29

SR Realization of the 1111 Recognizer
Figure 8.30

Clocked T and JK Realizations of the 1111 Recognizer
Figure 8.31

Clocked JK Flip-Flop Realization of a 1111 Recognizer
Figure 8.32

Design of a 0010 Recognizer Figure 8.33

Design of a Serial Binary Adder
Figure 8.34

Design of a Four-State Up/Down Counter
Figure 8.35

An Implementation of the Up/Down Counter
Figure 8.36

Design a BCD Counter Figure 8.37 (a) and (b)

Design of the BCD Counter (con’t)
Figure 8.37 (c)

Realization of the BCD Counter Design
Figure 8.37 (d) and (e)

K-map For Y1 in Example 8.16 Figure 8.38

Robot Controller Floor Plan -- Example 8.17
Figure 8.39

Robot Controller Design
Figure 8.40 (a) -- (e)

Robot Controller Realization
Figure 8.40 (f)

Candy Machine Controller Design -- Example 8.18
Figure 8.41

Algorithmic State Machines (ASMs)
Figure 8.42

ASM Representation of a Mealy Machine
Figure 8.43

ASM Representation of a Moore Machine
Figure 8.44

Eight-Bit Two’s Complementer ASM -- Example 8.19
Figure 8.45

Binary Multiplier Controller -- Example 8.20
Figure 8.46

One-Hot State Assignments
Table 8.1

ASM Design Using One-Hot State Assignments
Figure 8.47 (a) -- (b)

ASM Design Using One-Hot Assignments (con’t)
Figure 8.47 (c)

One-hot Design of A Multiplier Controller -- Example 8.21
Figure 8.48

Incompletely Specified Circuits -- Detonator (Example 8.22)
Figure 8.49

Detonator Example K-maps
Figure 8.50

Detonator Realization
Figure 8.51

Sate Assignments and Circuit Realization
Figure 8.52

Chapter 9 -- Simplification of Sequential Circuits

Redundant States in Sequential Circuits
Removal of redundant states is important because Cost: the number of memory elements is directly related to the number of states Complexity: the more states the circuit contains, the more complex the design and implementation becomes Aids failure analysis: diagnostic routines are often predicated on the assumption that no redundant states exist

Equivalent States States S1, S2, …, Sj of a completely specified sequential circuit are said to be equivalent if and only if, for every possible input sequence, the same output sequence is produced by the circuit regardless of whether S1, S2, …, Sj is the initial state. Let Si and Sj be states of a completely specified sequential circuit. Let Sk and Sl be the next states of Si and Sj, respectively for input Ip. Si and Sj are equivalent if and only if for every possible Ip the following are conditions are satisfied. The outputs produced by Si and Sj are the same, The next states Sk and Sl are equivalent.

Equivalent States Illustration
Figure 9.1

Equivalence Relations
Equivalence relation: let R be a relation on a set S. R is an equivalence relation on S if and only if it is reflexive, symmetric, and transitive. An equivalence relation on a set partitions the set into disjoint equivalence classes. Example: let S = {A,B,C,D,E,F,G,H} and R = {(A,A),(B,B),(B,H),(C,C),(D,D),(D,E),(E,E),(E,D),(F,F),(G,G),(H,H), (H,B)}. Then P = (A)(BH)(C)(DE)(F)(G) Theorem: state equivalence in a sequential circuit is an equivalence relation on the set of states. Theorem: the equivalence classes defined by the state equivalence of a sequential circuit can be used as the states in an equivalent circuit.

Methods for Finding Equivalent States
Inspection Partitioning Implication Tables

Finding Equivalent States By Inspection
Figure 9.2

Finding Equivalent States by Partitioning
Figure 9.3

Example 9.2 -- Partitioning example
Figure 9.4

Example 9.3 -- Another partitioning example
Figure 9.5

Example 9.4 -- Yet another partitioning example
Figure 9.6

Finding Equivalent States by Implication Tables
Figure 9.7

Example 9.5 -- Using implication tables to find equivalent states
Figure 9.8

Example 9.6 -- An implication table example

Incompletely Specified Circuits
Next states and/or outputs are not specified for all states Applicable input sequences: an input sequence is applicable to state, Si, of an incompletely specified circuit if and only if when the circuit is in state Si and the input sequence is applied, all next states are specified except for possible the last input of the sequence. Compatible states: two states Si and Sj are compatible if and only if for each input sequence applicable to both states the same output sequence will be produced when the outputs are specified. Compatible states: two states Si and Sj are compatible if and only if the following conditions are satisfied for any possible input Ip The outputs produced by Si and Sj are the same, when both are specified The next states Sk and Sl are compatible, when both are specified. Incompatible states: two states are said to be incompatible if they are not compatible.

Compatibility Relations
Compatibility relation: let R be a relation on a set S. R is a compatibility relation on S if and only if it is reflexive and symmetric. A compatibility relation on a set partitions the set into compatibility classes. They are typically not disjoint. Example: let S = {A,B,C,D,E} and R = {A,A),(B,B),(C,C),(D,D),(E,E),(A,B),(B,A),(A,C),(C,A), (A,D), (D,A),(A,E),(E,A),(B,D),(D,B),(C,D),(D,C),(C,E),(E,C)} Then the compatibility classes are (AB)(AC)(AD)(AE)(BD)(CD)(CE)(ABD)(ACD)(ACE) The incompatibility classes are (BC)(BE)(DE) Compatible pairs may be found using implication tables Maximal compatibles may be found using merger diagrams

Examples 9.8 and 9.9 -- Generating Maximal Compatibles and Incompatibles

Merger diagrams Figure 9.11

Example 9.10 -- Merger diagrams for example 9.8
Figure 9.12

Minimization Procedure
Select a set of compatibility classes so that the following conditions are satisfied Completeness: all states of the original machine must be covered Consistency: the chosen set of compatibility classes must be closed Minimality: the smallest number of compatibility classes is used

Bounding the number of states
Let U be the upper bound on the number of states needed in the minimized circuit Then U = minimum (NSMC, NSOC) where NSMC = the number of sets of maximal compatibles and NSOC = the number of states in the original circuit Let L be the lower bound on the number of states needed in the minimized circuit Then L = maximum(NSMI1, NSMI2,…, NSMIi) where NSMIi = the number of states in the ith group of the set of maximal incompatibles of the original circuit.

State Reduction Algorithm
Step find the maximal compatibles Step 2 -- find the maximal incompatibles Step 3 -- Find the upper and lower bounds on the number of states needed Step 4 -- Find a set of compatibility classes that is complete, consistent, and minimal Step 5 -- Produce the minimum state table

Example 9.11 -- Reduced state table corresponding to example 9.8
Figure 9.13

Example 9.12 -- State reduction problem
Figure 9.14

Example 9.13 -- Another state table reduction problem
Figure 9.15

Example 9.14 -- Yet another state reduction problem
Figure 9.16

Example 9.15 -- Optimal state assignments
Figure 9.17

Unique State Assignments for Four States
Figure 9.18

State Assignments for a Four State Machine
Figure 9.19

D flip-flop realization for assignment 1
Figure 9.20

Figure 9.21

Figure 9.22

State adjacencies for four-state assignments
Figure 9.23

Example 9.18 -- Implication Graphs
Figure 9.24

Example 9.19 -- Closed subgraphs
Figure 9.24

Example 9.20 -- Optimal state assignment
Figure 9.26

Example 9.21 -- Another state assignment problem
Figure 9.27

A D flip-flop realization of the previous example
Figure 9.28

Example 9.24 -- Closed partitions
Figure 9.29

Example 9.25 -- Cross dependency
Figure 9.30

Chapter 1 Number Systems and Codes

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