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Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56

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1 Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56
Prepared By: Aswini N, Praphul M N Department: ECE Date: 10/11/2014 Engineered for Tomorrow Prepared by : MN PRAPHUL & ASWINI N Assistant professor ECE Department Date : 11/10/14

2 syllabus Unit-1 : Basic Cmos Technology. 3 hrs
Engineered for Tomorrow syllabus Unit-1 : Basic Cmos Technology hrs Mos transistor theory hrs Unit-2 : Circuit Design Process hrs Unit-3 : Cmos Logic Structures hrs Unit-4 : Basic circuit concepts hrs Scaling of MOS circuits hrs Unit-5 : CMOS Subsystem design hrs Clocking stratagies hrs Unit-6 : CMOS Subsystem design process hrs Unit-7 : Memory,registers and clock hrs Unit Testability hrs

3 Engineered for Tomorrow
Hello friends!.. you are on a way to understand one of the most fascinating fields of modern times.Welcome to the world of VLSI.

4 a.Basic MOS Technology b.MOS transistor theory
Engineered for Tomorrow Unit 1 a.Basic MOS Technology b.MOS transistor theory

5 Syllabus Integrated Circuit’s era.
Engineered for Tomorrow Syllabus Integrated Circuit’s era. Enhancement and Depletion mode MOS transistors. Nmos Fabrication CMOS Fabrication. Thermal aspects of Processing BICMOS technology Production of E-beam masks

6 Integrated Circuit’s era
Engineered for Tomorrow Integrated Circuit’s era What is an IC?? IC is abbreviated as Integrated circuit.IC consists of an electronic switching networks that are created on small area of a silicon wafer using a complex set of physical and chemical processes. Transistors are used as switching components. Transistor was first invented by William.B.ShockleyWalter Brattain and John Bardeenof Bell Labratories. In 1961, first IC was introduced.

7 Levels of transistors integrated
Engineered for Tomorrow Levels of transistors integrated Level of integration Number of transistors Examples SSI(Small Scale Integration) transistors Logic gates MSI(Medium Scale Integration) transistors counters LSI(Large Scale Integration) transistors 8-bit chip VLSI(Very Large Scale Integration) transistors Example:16 & 32 bit microprocessors ULSI(Ultra Large Scale Integration) transistors DSP’s, virtual reality machines, smart sensors

8 Engineered for Tomorrow
Moore’s Law “The number of transistors embedded on the chip doubles after every one and a half years.” ---Gordon Moore, cofounder Intel Corporation Fig 1. Moore's graph

9 Types of Field Effect Transistors (The Classification)
Engineered for Tomorrow Types of Field Effect Transistors (The Classification)

10 Field-Effect Transistor (FET)
Engineered for Tomorrow Field-Effect Transistor (FET) Metal-oxide semiconductor field-effect transistor (MOSFET) has been extremely popular since the late 1970s. Compared to BJTs, MOS transistors: Can be made smaller /higher integration scale Easier to fabricate /lower manufacturing cost Simpler circuitry for digital logic and memory Inferior analog circuit performance (lower gain) Most digital ICs use MOS technology

11 MOS Transistors Fig 2. CROSS-SECTION of NMOS Transistor n+ p-substrate
Engineered for Tomorrow MOS Transistors n+ p-substrate Field-Oxide (SiO 2 ) p+ stopper Polysilicon Gate Oxide Drain Source Gate Bulk Contact Fig 2. CROSS-SECTION of NMOS Transistor

12 MOS transistors Symbols
Engineered for Tomorrow MOS transistors Symbols

13 Switch Model of NMOS Transistor
Engineered for Tomorrow Switch Model of NMOS Transistor Gate Source (of carriers) Drain | VGS | | VGS | < | VT | | VGS | > | VT | Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) Ron

14 Switch Model of PMOS Transistor
Engineered for Tomorrow Switch Model of PMOS Transistor Gate Source (of carriers) Drain | VGS | | VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| | Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’) Ron

15 MOSFETs- Enhancement Type
Engineered for Tomorrow MOSFETs- Enhancement Type The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

16 Physical Operation of Enhancement MOSFET
Engineered for Tomorrow Physical Operation of Enhancement MOSFET If S and D are grounded and a positive voltage is applied to G, the holes are repelled from the channel region downwards, leaving behind a carrier-depletion region. Further increasing VG attracts minority carrier ( electrons) from the substrate into the channel region. When sufficient amount of electrons accumulate near the surface of the substrate under the gate, an n region is created-called as the inversion layer.

17 N-Channel enhancement mode
Engineered for Tomorrow N-Channel enhancement mode

18 p-channel enhancement mode
Engineered for Tomorrow p-channel enhancement mode Output characteristics Transfer characteristics

19 Field-Effect Transistors (FETs) Depletion Type
Engineered for Tomorrow Field-Effect Transistors (FETs) Depletion Type The depletion type MOSFET has similar structure to that the enhancement type MOSFET but with one important difference The depletion MOSFET has a physically implanted channel. Thus an n-channel depletion-type MOSFET has an n-type silicone region connecting the source and drain (both +n) at the top of the type substrate. The channel depth and hence its conductivity is controlled by vGS. Applying a positive vGS enhances the channel by attracting more electrons. The reverse when applying negative volt. The negative voltage is said to deplete the channel (depletion mode).

20 p and n channel depletion mode characteristics
Engineered for Tomorrow p and n channel depletion mode characteristics

21 MOS transistor action Three distinct region Cutoff region
Engineered for Tomorrow MOS transistor action Three distinct region Cutoff region Linear region Saturation region.

22 Cutoff Region VGS < VT0 Assume n-channel MOSFET and VSB=0
Engineered for Tomorrow Cutoff Region Assume n-channel MOSFET and VSB=0 Cutoff Mode: 0≤VGS<VT0 The channel region is depleted and no current can flow gate drain source IDS=0 VGS < VT0

23 Linear Region VDS < VGS – VT0
Engineered for Tomorrow Linear Region Linear (Active, Triode) Mode: VGS≥VT0, 0≤VDS≤VD(SAT) Inversion has occurred; a channel has formed For VDS>0, a current proportional to VDS flows from source to drain Behaves like a voltage-controlled resistance gate drain source current IDS VDS < VGS – VT0

24 Engineered for Tomorrow
Pinch-Off Pinch-Off Point (Edge of Saturation) : VGS≥VT0, VDS=VD(SAT) Channel just reaches the drain Channel is reduced to zero inversion charge at the drain Drifting of electrons through the depletion region between the channel and drain has begun gate drain source current IDS VDS = VGS – VT0

25 Saturation VDS > VGS – VT0 Saturation Mode: VGS≥VT0, VDS≥VD(SAT)
Engineered for Tomorrow Saturation Saturation Mode: VGS≥VT0, VDS≥VD(SAT) Channel ends before reaching the drain Electrons drift, usually reaching the drift velocity limit, across the depletion region to the drain Drift due to high E-field produced by the potential VDS-VD(SAT) between the drain and the end of the channel gate drain source IDS VDS > VGS – VT0

26 Nmos/Cmos Fabrication Process
Engineered for Tomorrow Nmos/Cmos Fabrication Process Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2

27 Oxidation Grow SiO2 on top of Si wafer
Engineered for Tomorrow Oxidation Grow SiO2 on top of Si wafer 900 – 1200 C with H2O or O2 in oxidation furnace

28 Photoresist Spin on photoresist
Engineered for Tomorrow Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light

29 Lithography Expose photoresist through n-well mask
Engineered for Tomorrow Lithography Expose photoresist through n-well mask Strip off exposed photoresist

30 Etch Etch oxide with hydrofluoric acid (HF)
Engineered for Tomorrow Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

31 Strip Photoresist Strip off remaining photoresist
Engineered for Tomorrow Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step

32 Polysilicon Deposit very thin layer of gate oxide
Engineered for Tomorrow Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor

33 Polysilicon Patterning
Engineered for Tomorrow Polysilicon Patterning Use same lithography process to pattern polysilicon

34 Engineered for Tomorrow
Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

35 N-diffusion Pattern oxide and form n+ regions
Engineered for Tomorrow N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

36 N-diffusion cont… Strip off oxide to complete patterning step
Engineered for Tomorrow N-diffusion cont… Strip off oxide to complete patterning step

37 Engineered for Tomorrow
P-Diffusion Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

38 Engineered for Tomorrow
Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

39 Metallization Sputter on aluminum over whole wafer
Engineered for Tomorrow Metallization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

40 Engineered for Tomorrow
Bicmos technology BiCMOS' is an evolved semiconductor technology that integrates two formerly separate semiconductor technologies - those of the bipolar junction transistor and the CMOS transistor - in a single integrated circuit device. Bipolar junction transistors offer high speed, high gain, and low output resistance, which are excellent properties for high-frequency analog amplifiers. CMOS technology offers high input resistance and is excellent for constructing simple, low-power logic gates.

41 Engineered for Tomorrow
Bicmos structure

42 Bicmos technology process
Engineered for Tomorrow Bicmos technology process

43 Threshold voltage (Vt)
Engineered for Tomorrow Threshold voltage (Vt) The voltage at which an MOS device begins to conduct ("turn on") is a threshold voltage. The threshold voltage is a function of following parameters: Gate conductor material Gate insulator material Gate insulator thickness Impurity at the silicon-insulator interface Voltage between the source and the substrate Vsb Temperature

44 Second Order Effects Threshold voltage – Body effect
Engineered for Tomorrow Second Order Effects Threshold voltage – Body effect Subthreshold region Channel length modulation Mobility variation Fowler_Nordheim Tunneling Drain Punchthrough Impact Ionization – Hot Electrons

45 Sub-Threshold Behavior
Engineered for Tomorrow Sub-Threshold Behavior For gate voltage less than the threshold – weak inversion Diffusion is dominant current mechanism (not drift) Sub-threshold current is exponential function of applied gate voltage Sub-threshold current gets larger for smaller gates (L)

46 Channel Length Modulation
Engineered for Tomorrow Channel Length Modulation With pinch-off the channel at the point y such that Vc(y)=VGS - VT0, The effective channel length is equal to L’ = L – ΔL ΔL is the length of channel segment over which QI=0. Place L’ in the ID(SAT) equation: Fig2 .Illustrating channel length modulation

47 Mobility Drain current model assumed constant mobility in channel
Engineered for Tomorrow Mobility Drain current model assumed constant mobility in channel Mobility of channel less than bulk – surface scattering Mobility depends on gate voltage – carriers in inversion channel are attracted to gate – increased surface scattering – reduced mobility

48 Engineered for Tomorrow
Drain punch through Punch through in a MOSFET is an extreme case of channel length modulation where the depletion layers around the drain and source regions merge into a single depletion region. The field underneath the gate then becomes strongly dependent on the drain-source voltage, as is the drain current. Punch through causes a rapidly increasing current with increasing drain-source voltage. This effect is undesirable as it increases the output conductance and limits the maximum operating voltage of the device

49 CMOS(Complementary metal oxide semiconductor)
Engineered for Tomorrow CMOS(Complementary metal oxide semiconductor) NOT gate (inverter)

50 Engineered for Tomorrow
CMOS Vout = 0 Vin = 1 Vout = 1 Vin = 0

51 Cmos Inverter Dc Characteristics
Engineered for Tomorrow Cmos Inverter Dc Characteristics Figure shows five regions namely region A, B, C, D & E. also we have shown a dotted curve which is the current that is drawn by the inverter.

52 Engineered for Tomorrow
Region A The output in this region is High because the P device is OFF and n device is ON. In region A, NMOS is cutoff region and PMOS is on, therefore output is logic high. Fig 3.Ciruit illustrating Region a

53 Region B: Equivalent circuit in Region B
Engineered for Tomorrow Region B: Equivalent circuit in Region B In this region PMOS :linear region and NMOS: saturation region. The expression for the NMOS current is PMOS current is Fig 4.Ciruit illustrating Region B Output voltage is

54 Region C: Both n and p transistors :saturation region.
Engineered for Tomorrow Region C: Equivalent circuit in Region C Both n and p transistors :saturation region. we can equate both the currents and we can obtain the expression for the mid point voltage or switching point voltage of a inverter. The corresponding equations for nmos, pmos and switching point are as follows: Fig 5.Ciruit illustrating Region C

55 Region D P transistor :saturation region n transistor :linear region
Engineered for Tomorrow Region D P transistor :saturation region n transistor :linear region Fig 6.Ciruit illustrating Region D

56 7.1.5 Region E: The output in this region is zero.
Engineered for Tomorrow 7.1.5 Region E: The output in this region is zero. P device :OFF and n device : ON. Fig 7.Ciruit illustrating Region E

57 Influence of ßn/ßp on the VTC characteristics:
Engineered for Tomorrow Influence of ßn/ßp on the VTC characteristics: The characteristics shifts left if the ratio of ßn/ßp is greater than 1(say 10). The curve shifts right if the ratio of ßn/ßp is lesser than 1(say 0.1).

58 Engineered for Tomorrow
Noise Margin: Noise margin is a parameter related to input output characteristics. It determines the allowable noise voltage on the input so that the output is not affected. We will specify it in terms of two things: LOW noise margin NM L =|VILmax – VOLmax| HIGH noise margin NMH=|Vohmin – VIHmin|

59 Static Load MOS inverters
Engineered for Tomorrow Static Load MOS inverters This circuit uses a resistive load and current source load inverter. Usually resistive load inverters are not preferred because of the power consumption and area issues.

60 Pseudo-NMOS inverter:
Engineered for Tomorrow Pseudo-NMOS inverter: This circuit uses the load device which is p device and is made to turn on always by connecting the gate terminal to the ground. Power consumption is High compared to CMOS inverter particularly when NMOS device is ON because the p load device is always ON.

61 Saturated load inverter:
Engineered for Tomorrow Saturated load inverter: The load device is an nMOS transistor in the saturated load inverter. This type of inverter was used in nMOS technologies prior to the availability of nMOS depletion loads.

62 Pass transistors We have n and p pass transistors.
Engineered for Tomorrow Pass transistors We have n and p pass transistors. N pass transistor p pass transistor

63 Transmission gates(TGs)
Engineered for Tomorrow Transmission gates(TGs) It’s a parallel combination of pmos and nmos transistor with the gates connected to a complementary input. The disadvantages weak 0 and weak 1 can be overcome by using a TG instead of pass transistors. When ¢=’0’ n and p device off, Vin=0 or 1, Vo=’Z’ ¢=’1’ n and p device on, Vin=0 or 1, Vo=0 or 1 , where ‘Z’ is high impedance.

64 Engineered for Tomorrow
Tristate Inverter: By cascading a transmission gate with an inverter the tristate inverter circuit can be obtained. The working can be explained with the help of the circuit. The two circuits are the same only difference is the way they are written. When CL is zero the output of the inverter is in tristate condition. When CL is high the output is Z is the inversion of the input A

65 Production of E-beam masks
Engineered for Tomorrow Production of E-beam masks

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