1. Optimisation of electrical injection in large area top-emitting VCSELs for Cavity Solitons
OUTLINE
1. Electrical simulation of VCSELs :
standard structures
technological solutions : tunnel junction
ITO cap layer
local injection
Electrical measurement of Esaki junctions
ITO Study: deposition parameters, optical and electrical properties
Local injection apertures by planar oxidation
Design of devoted devices

2. Previous measurements of large area VCSELs
Previous large area VCSEL
(Standard structure)
AB Light intensity profile
IL max
100µm A B
IL min
Inhomogeneous light intensity : ratio = 2 (Under Laser threshold)

3. Electrical simulations of large area VCSELs
Cylindrical symetry of VCSEL  half-device 2D simulation
N-DBR
Buried
Oxide
} Cavity + MQW
Anode
Cathode
P-DBR
Large area VCSEL Standard structure
Anode
100 µm
1. Electrical simulations of large area VCSELs
120 µm
Simulations used :
Blaze / ATLAS / Silvaco
+ database derived from our measurements and bibliography

4. Standard VCSEL structure
AB current & carrier density profiles
Anode
Cap layer P+
1. Electrical simulations of large area VCSELs
P-DBR A B
N-DBR
Cathode
Inhomogeneous carrier density in the active zone : ratio = 2

5. VCSEL with Esaki junction (λ/4n)
Cap layer : GaAs N+ /P+
current & carrier density profiles in MQW
1. Electrical simulations of large area VCSELs
Inhomogeneous carrier density in the active zone : ratio = 1.56

6. VCSEL with ITO layer (250nm)
Cavity + MQW
Anode
Cathode
P-DBR
N-DBR
Oxide
ITO layer
current & carrier density profiles in MQW
1. Electrical simulations of large area VCSELs
Improved carrier distribution in the active zone : ratio = 1.6

7. VCSEL with local injection apertures
Anode
Localized oxides
Oxide
apertures
1. Electrical simulations of Large area VCSELs
Eq. P-DBR
} Cavity + MQW
Eq. N-DBR
Cathode

8. VCSEL with local injection
current & carrier density profile in MQW
Cavity + MQW
Anode
Cathode
P-DBR
N-DBR
Localized
oxides
1. Electrical simulations of Large area VCSELs
Flat carrier density in the active zone: ratio = 1.06

9. Electrical characterization
GaAs Homojunction (N+ / P+ => Zener breakdown )
Zener voltage measurements
ATLAS Simulation :
I(V) curve
of structure A
(V)
(A)
Forward
Reverse N+ P+
2. Esaki junction
J = 1 kA/cm²
1kA/cm²
NA (Be) (cm-3)
ND (Si)
(cm-3)
depletion zone (nm)
BVZ (V)
Atlas calculations
Measurements
Struct.A
3 1018 25
1.06
2.8
Struct. B
1 1018
100
5.36
4.8
Struct. C
5 1017
depleted
10.1
5.8
Struct.D 38
1.63
2.7
Epitaxy and
fabrication
of test structures

10. Sputtering parameters for ITO deposition
Deposition process: Reactive DC sputtering of ITO target (In90%Sn10%)
critical parameters:
Plasma power
Target to sample distance
DC bias
Gas partial pressure: O2, Ar
Post annealing
3. ITO Study
Deposited chemical composition:
Non-stochiometric oxide
In2-xSnxO3+-δ
column-like structure (crystal with a high density of sub-boundaries + amorphous phases)
Ref : David Vaufrey, Thèse
ECOLE CENTRALE DE LYON
2003

11. Electrical & optical Properties of deposited ITO
nITO=2  aimed thickness : 212nm (l/2n)
Study of deposition parameters
Thickness vs Pressure
ITO electrical properties strongly depend on the annealing process:
Optimal deposition parameters:
Plasma power = 200W
Target to sample distance = 75mm
DC bias = - 60V
Gas partial pressure: O2 = 1sccm, Ar=10sccm
3. ITO Study

12. Electrical & optical Properties of deposited ITO
Optical transmission spectrum
Current layer properties:
Deposition rate: 73nm/mn
Resistivity: Ω.cm (50Ω/ٱ for 220nm-thickness layer)
Transmission>98% at 850nm for 220nm-thickness layer
Successful test of ITO lift-off process: Technological step ready to use
850nm
3. ITO Study

13. Local injection apertures by planar oxidation
Patent n° FR (Fév. 2005)
Lithography +
Diffusion mask etch
Planar oxidation
Localized oxide islands
Epitaxial regrowth
or ITO deposition
AlAs or GaAlAs
GaAs
4. Planar oxidation
Advantages of this new approach :
- Full and accurate control of oxidized patterns (multi-scale)
fully planar devices
carrier injection « engineering »
localisation of the injection depends on the vertical positionning relatively to the cavity position
In progress

14. 5. Design of devoted devices
Standard structure
(reference)
5. Design of devoted devices

15. Metallic grid anode electrode
5. Design of devoted devices
3µm
17 µm

16. 5. Design of devoted devices
ITO cap layer
5. Design of devoted devices

17. ITO cap layer + lateral contact
5. Design of devoted devices

18. Local injection + ITO cap layer
5. Design of devoted devices

19. Electrical manipulation of Solitons
5. Design of devoted devices
IA > IB lateral displacement
IA < IB lateral displacement

20. Conclusion, outlook Conclusions :
Esaki junction : excessive drop voltage (> 2.7V) due to low N-doping
(level obtained by MBE)
Study of ITO films: deposition and annealing optimisation to improve :
T > 95% R = 50/
Planar oxidation : in progress for a better control of oxide aperture dimensions (~1µm) and epitaxial regrowth
device design : in progress
Conclusion, outlook
Future work :
Finalize photolithography masks
Test and improve the fabrication process
Devices test : LED test structures, then on VCSELs layers