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CPU Organisation & Operation

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1 CPU Organisation & Operation
Professor Kin K. Leung Heavily based on materials by Dr. Naranker Dulay

2 Fetch-Execute Cycle Fetch the Instruction
Increment the Program Counter Decode the Instruction Fetch the Operands Perform the Operation Store the Results Repeat Forever

3 High-Level/Low-Level Languages, Machine Code
High-Level Language (e.g. Java, C++, Haskell) A = B + C Assignment Statement Low-Level Language -> Assembly Language (e.g. Pentium, PowerPC, ARM etc, Java Bytecode) LOAD R2, B Assembly Language ADD R2, C Instructions STORE R2, A (Binary) Machine Code Machine Code Instructions

4 The Toy1 Architecture Maximum of 1024 x 16-bit memory words Memory is Word Addressed Two’s Complement Integer Representation 4 General Purpose Registers (16-bit) : R0, R1, R2, R3 Upto 16 “Instructions”, e.g. LOAD, ADD, STORE

5 Toy1 Instruction Set LOAD Register , [MemoryAddress] Register = Memory [MemoryAddress] STORE Register , [MemoryAddress] Memory [MemoryAddress] = Register ADD Register , [MemoryAddress] Register = Register + Memory [MemoryAddress] SUB Register , [MemoryAddress] Register = Register - Memory [MemoryAddress]

6 Toy1 Instruction Format
ADD R2, C Assembly Instruction e.g. Machine Code 4-bit OPCODE 2-bit REG ADDRESS 10-bit Instruction Fields OPeration CODE (Selects CPU Instruction) REGister (Specifies 1st Operand for Instruction) ADDRESS (Specifies 2nd Operand for Instruction)

7 Other Possibilities for the Format
OPCODE ADDRESS REG ADD R2, C 4-bit 10-bit 2-bit REG ADDRESS OPCODE 2-bit 10-bit 4-bit ADD R2, R3 REG 4-bit 2-bit OPCODE

8 Instruction Field Encoding
OPCODE REG ADDRESS 4-bit 2-bit 10-bit 16-bit Instruction OPCODE LOAD (4-bit) STORE ADD SUB 0100 REG Register 0 00 (2-bit) Register Register Register 3 11 ADDRESS 10-bit Memory Word Address

9 Memory Placement (Program)
Assembly Instruction Machine Instruction OP REG ADDRESS H Memory Address LOAD R2, [201H] 0001 10 1 A 1 ADD R2, [202H] 0011 10 H 3 A 2 STORE R2, [200H] H 0010 10 2 A MEMORY

10 Memory Placement (Data)
Assembly Instruction Data Memory Address MEMORY A = 0 H H B = 9 H C = 6

11 CPU Organisation CPU RAM R0 R1 R2 R3 I n t e r n a l B u s Address Bus
3FD 3FE 3FF R0 R1 R2 R3 I n t e r n a l B u s Address Bus ALU Output Reg Input Reg1 Input Reg2 Data Bus Control Bus Program Counter Instr. Decoder Instr. Register Control Unit

12 LOAD R2, [201H] R2=Memory[201H] CPU RAM 080H R2 ALU 080H 080H PC 080H
3FD 3FE 3FF 080H R2 ALU 080H 080H PC 080H Instr. Decoder Control Unit 1

13 LOAD R2, [201H] R2=Memory[201H] CPU RAM 080H R2 ALU PC 080H + 1
3FD 3FE 3FF 080H R2 ALU PC 080H + 1 Instr. Decoder Control Unit 2

14 LOAD R2, [201H] R2=Memory[201H] CPU RAM 080H R2 ALU PC 081H
3FD 3FE 3FF 080H R2 ALU PC 081H Instr. Decoder Control Unit 3

15 LOAD R2, [201H] R2=Memory[201H] CPU 080H R2 ALU RAM PC 081H
080H R2 1A01 3A02H 2A00H 0000 0009 0006 1A01H ALU RAM PC 081H Instr. Decoder 3FD 3FE 3FF Control Unit 4

16 LOAD R2, [201H] R2=Memory[201H] CPU 201H R2 ALU 201H RAM 1A01H PC 081H
201H R2 1A01H 3A02H ALU 201H 2A00H 1A01H 1A01 RAM 1A01H 0000 0009 PC 081H 0006 1A01H 1A01H 1A01H 3FD 3FE 3FF 1, 2, 201H 201H 1, 2, 201H 5

17 LOAD R2, [201H] R2=Memory[201H] CPU 201H 201H R2 0009 ALU 0009 0009
201H 201H 0009 R2 0009 1A01H 3A02H ALU 0009 2A00H 0009 0009 RAM 0000 0009 0009 PC 081H 0006 1A01H 3FD 3FE 3FF 1, 2, 201H 6

18 ADD R2, [202H] R2=R2+Memory[202H]
CPU 081H R2 0009 1A01H 3A02H ALU 081H 2A00H RAM 0000 081H 0009 PC 081H 0006 3FD 3FE 3FF 7

19 ADD R2, [202H] R2=R2+Memory[202H]
CPU 081H R2 0009 1A01H 3A02H ALU 2A00H RAM 0000 0009 PC 081H + 1 0006 3FD 3FE 3FF 8

20 ADD R2, [202H] R2=R2+Memory[202H]
CPU 081H 202H 0009 R2 0009 0009 0009 1A01H 3A02H 3A02 ALU 0009 2A00H 0009 202H 3A02H 3A02H RAM 3A02H 0000 0009 PC 082H 0006 3A02H 3A02H 3A02H 3FD 3FE 3FF 3, 2, 202H 202H 3, 2, 202H 9

21 ADD R2, [202H] R2=R2+Memory[202H]
CPU 202H 202H 000FH R2 000FH 0009 1A01 000FH 3A02 ALU 2A00 0009 0006 0006 000FH ADD RAM 0006 000FH 0006 000FH 0000 0009 PC 082H 0006 0006 3A02H 3FD 3FE 3FF 3, 2, 202H 10

22 STORE R2, [200H] Memory[200H]=R2
CPU 082H R2 000FH 1A01H 3A02H ALU 082H 2A00H RAM 0000 082H 0009 PC 082H 0006 3FD 3FE 3FF 11

23 STORE R2, [200H] Memory[200H]=R2
CPU 082H R2 000FH 1A01H 3A02H ALU 2A00H RAM 0000 0009 PC 082H + 1 0006 3FD 3FE 3FF 12

24 STORE R2, [200H] Memory[200H]=R2
CPU 082H 1 200H 000FH R2 000FH 000F 000FH 1A01H 3A02H ALU 2A00H 2A00 200H 000FH 2A00H RAM 2A00H 0000 0009 PC 083H 1 0006 2A00H 2A00H 2A00H 1 3FD 3FE 3FF 2, 2, 200H 200H 2, 2, 200H 1 13

25 STORE R2, [200H] Memory[200H]=R2
CPU 00FH 200H 1 00FH 200H 1 R2 000FH 1A01H 3A02H ALU 2A00H RAM 000FH 0000 0009 PC 083H 0006 3FD 3FE 3FF 14

26 Think About Fetch-Execute Cycle Assembly Languages
Program Representation: Instructions, Instruction Fields, Instruction Formats CPU Components: Registers, ALU, Control Unit Registers: General Purpose Registers, Program Counter (PC), Instruction Register (IR), ALU Registers Buses: Internal, Address, Data, Control Next Topic TOY1 Assembly Programming

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