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Pixel panels and CMOS Read-out electronics

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Presentation on theme: "Pixel panels and CMOS Read-out electronics"— Presentation transcript:

1 Pixel panels and CMOS Read-out electronics
Jan Timmermans - NIKHEF 25-26 Feb 2008 LP-TPC subsystems meeting

2 LP-TPC subsystems meeting
A 5 cm3 TPC (two electron tracks from 90Sr source) 25-26 Feb 2008 LP-TPC subsystems meeting

3 LP-TPC subsystems meeting
Pixel systems sofar…. Timepix (+ Medipix2) with triple-GEMs (Freiburg, Bonn) Timepix (+ Medipix2) with single Micromegas (NIKHEF, Saclay) Now: Timepix + amorphous Si (highly resistive) + integrated grid (Ingrid) (NIKHEF), soon also Saclay larger drift lengths, up to 100 mm 25-26 Feb 2008 LP-TPC subsystems meeting

4 LP-TPC subsystems meeting
Sofar single-chip systems used Soon (Eudet deliverable) small multi-chip systems: Bonn: two 4-chip boards  on endplate module Saclay: one 8-chip board  on endplate module NIKHEF: 4-chip board, fitting single-chip detector mechanics and drifter (could become endplate module) Later (~3/2009): aim for a 64-chip system (NIKHEF; may be too ambitious; bottleneck could be production of sufficient # Ingrids) 25-26 Feb 2008 LP-TPC subsystems meeting

5 Current readout Timepix
Two interface types: Muros 2.1: rather “bulky” maximum rate ~20-40 Hz for one chip currently no further stock! (NIKHEF has 3) USB1.2 (Prague): can now handle Timepix rather slow: few Hz for one chip (USB-2 is under development at Prague; available this summer?) 25-26 Feb 2008 LP-TPC subsystems meeting

6 LP-TPC subsystems meeting
25-26 Feb 2008 LP-TPC subsystems meeting

7 LP-TPC subsystems meeting
NIKHEF setup (> 22 Aug. 2007) Next-3 Next-1,2 “old” 25-26 Feb 2008 LP-TPC subsystems meeting

8 LP-TPC subsystems meeting
1 connector + External Ultra SCSI cable (68 pins) for each ‘group’ of Timepix chips (has magnetic connector shielding!) cable length <~ 1m National Instruments DIO-653X card cable length 1-2 m Muros  PC have not yet checked these connectors DAQ on Windows PC with Pixelman software; Bonn/Freiburg working on triggering PC. Muros is externally triggered 25-26 Feb 2008 LP-TPC subsystems meeting

9 Possible fast readout larger systems
25-26 Feb 2008 LP-TPC subsystems meeting

10 RELAXD Quad Board Project
Overview By: Bas van der Heijden Thanks to: Jan Visschers Lukas Tomasek Hans Verkooijen John Hug 25-26 Feb 2008 LP-TPC subsystems meeting 10 10

11 LP-TPC subsystems meeting
Within the RELAXD project: Development of through-Si via connections to backside of chip (in collaboration with IMEC Leuven) Fast “5Gb” readout: Development of quad carrier board Development of slave board For LP-TPC need active cooling: ~1W/chip 25-26 Feb 2008 LP-TPC subsystems meeting

12 LP-TPC subsystems meeting
Quad carrier board Relaxd Slaveboard 25-26 Feb 2008 LP-TPC subsystems meeting 12 12

13 Slaveboard layout and dimensions
Lattice SC15 FPGA Dimensions: 3cm x 8.3cm 100p Side entry connector Medipix Power supply’s OSCILLATOR: 156.25MHz for 3Gig 8b10b 125MHz for GbEthernet JTAG + Test pins RJ45 2x LVDS + power 25-26 Feb 2008 LP-TPC subsystems meeting 13

14 Additional Slaveboard hardware
8 Mbit Flash memory VDD & VDDA Current measurement (2ch of the ADC) VDD & VDDA voltage measurement (2ch of the ADC) VDD & BIAS voltage adjust (2ch of the DAC) Quadboard temperature sensor FPGA core temperature sensor 10 Test pins & 4 led's 25-26 Feb 2008 LP-TPC subsystems meeting 14 14

15 LP-TPC subsystems meeting
25-26 Feb 2008 LP-TPC subsystems meeting 15

16 LP-TPC subsystems meeting
Communication scheme 1 Primary 3 Gb LVDS direct link PCI express card (lattice development board) 9 x Lattice SC15 MPIX 1 3Gb/s 8b10b LVDS MPIX 2 MPIX 3 MPIX 4 25-26 Feb 2008 LP-TPC subsystems meeting 16 16

17 LP-TPC subsystems meeting
Communication scheme 2 Secondary Gigabit Ethernet (UDP) Using Ethernet PHY (Marvell) MPIX 1 Lattice SC15 FPGA MPIX 2 MPIX 3 MPIX 4 Gigabit Ethernet PHY (Marvell) GMII 1.25GHz Ethernet 1GHz GbE core 25-26 Feb 2008 LP-TPC subsystems meeting 17 17

18 LP-TPC subsystems meeting
Summary Timepix pixel system can operate simultaneously with Micromegas panel(s) Several small scale 4-8 chip systems in preparation; should be available within ~2 months Larger (~64 chips, 128 cm2) system, late spring 2009; needs active cooling! Ambitious extension. 25-26 Feb 2008 LP-TPC subsystems meeting


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