1. System Programming and administration
Lecture 2
System Software and Machine Architecture

2. 2.1 System Software and Machine Architecture
Application Program v.s. System Software
Applications：focus on the particular application—machine independent
System Software：intend to support computer operations and uses—machine dependent

3. 2.1 System Software and Machine Architecture
Machine Dependent Features with S/S
Machine Architecture
Instruction formats
Addressing modes
The number of registers
The type of registers
….. and so on

4. 2.1 System Software and Machine Architecture
Machine Independent Features with S/S
The general design and logic of an assembler
Some of code optimization techniques
The process of linking independently assembled subprograms together

5. 2.2 Simplified Instructional Computer (SIC)
Two versions
SIC standard
SIC/XE (eXtra Equipment or eXtra Expansive)：upward compatible

6. 2.2.1 SIC Machine Architecture
Memory Features
8-bit bytes
Word - 3 bytes (24 bits)
Byte addressing
Total memory size -- 32KBytes (215)

7. 2.2.1 SIC Machine Architecture
Register Features
5 special registers (24 bits long for each)
Mnemonic
Number
Special use A
Accumulator X 1
Index register L 2
Linkage register PC 8
Program counter SW 9
Status word

8. 2.2.1 SIC Machine Architecture
Data Formats
Integer — 24-bit binary number
2’s complement representation is used for negative values
Character set — 8-bit ASCII code
No Floating-Point hardware support on the SIC standard version

9. 2.2.1 SIC Machine Architecture
Instruction Formats (Standard version) —24-bit format 15 x 8 1
opcode
address
Note that: The flag bit x is used to indicate indexed-addressing mode

10. 2.2.1 SIC Machine Architecture
Two Addressing Modes
Mode
Indication
Target address calculation
Direct
x=0
TA=address
Indexed
x=1
TA=address+(X)
Note that: ( ) means the contents of a register or a memory location

11. 2.2.1 SIC Machine Architecture
Instruction Set
LDA、LDX、STA (load and store register)
ADD、SUB、MUL、DIV ( +, -, *, / )
COMP、JLT、JGT、JEQ (compare, set condition code & jump)
JSUB 、RSUB (jump subroutine、return to the address contained in Register L)

12. 2.2.1 SIC Machine Architecture
Input & Output
Transfer 1 byte at a time to or from the rightmost 8-bits of register A
Each device is assigned a unique 8-bit code
Three I/O instructions
Test Device (TD): “<“ means the device is ready,
“=“ means the device is not ready
Read Data (RD)
Write Data (WD)

13. 2.2.2 SIC/XE Machine Architecture
Memory Features
The memory structure is the same as SIC standard version
8-bit bytes
Word—3 bytes (24 bits)
Byte addressing
Total Memory size : 1 MB (220)

14. 2.2.2 SIC/XE Machine Architecture
Registers: Four additional registers are provided
Mnemonic
Number
Special use A
Accumulator X 1
Index register L 2
Linkage register B 3
Base register S 4
General working register T 5 F 6
Floating-point accumulator (48 bits) PC 8
Program counter SW 9
Status word

15. 2.2.2 SIC/XE Machine Architecture
Data Formats
SIC/XE provides the same data formats as the SIC standard version
Integer—24-bit binary number
2’s complement representation is used for negative values
Character set — 8-bit ASCII code
Provides a 48-bit Floating-Point data type

16. 2.2.2 SIC/XE Machine Architecture
A 48-bit Floating-Point data type format
S: sign (0=positive, 1=negative)
Exponent (e) : 0 ~ 2047 (Excess-1024)
Fraction (f) : 0 ~ 1, the high-order bit must be 1 (similar to IBM format)
The absolute value = f * 2^(e-1024) 36
exponent 1 11 s
Fraction (mantissa)

17. 2.2.2 SIC/XE Machine Architecture
Instruction Formats – Four instruction formats are provided
Format 1 (1 byte) – do not reference memory at all 8
opcode
Format 2 (2 byte) – do not reference memory at all 8 4 4
opcode r1 r2

18. 2.2.2 SIC/XE Machine Architecture12
opcode
Format 3 (3 byte) 1 i n x p
e=0 b
displacement 6
Format 4 (4 byte) 20
opcode 1 i n x p
e=1 b
address 6

19. 2.2.2 SIC/XE Machine Architecture
Addressing Modes
2 new relative addressing modes are available with format 3 instructions
Mode
Indication
Target address calculation
Base relative
b=1, p=0
TA=(B) + displacement
(0 ≤ disp ≤ 4095)
Program-counter relative
b=0, p=1
TA=(PC) + displacement
(-2048≤ disp ≤ 2047)
Direct addressing
b=0, p=0
TA=displacement (disp)
Also for format 4

20. 2.2.2 SIC/XE Machine Architecture
Other aspects for memory addressing
Any of above addressing modes can also be combined with indexed addressing — i.e. if bit x =1 then
TA=TA+(X)
The standard SIC uses only direct addressing (with or without indexing)
Indexing cannot be used with immediate or indirect addressing modes

21. 2.2.2 SIC/XE Machine Architecture
Instruction Set
SIC/XE provides all of the instructions that are available on the standard version
Additional Instructions
Load register – LDB、STB
Floating-point operations -- ADDF、SUBF、MULF、DIVF
Register-to-register operations -- ADDR、SUBR、MULR、DIVR、RMO (register move)
Supervisor call -- SVC

22. 2.2.2 SIC/XE Machine Architecture
Input and Output
I/O instructions for SIC are also available on SIC/XE (TD, RD, WD)
I/O channels are used to perform I/O (i.e. allow overlay processing of computing and I/O)
I/O Instructions
SIO – Start I/O
TIO – Test I/O
HIO – Halt I/O operations

23. 2.2.3 SIC Programming
Fig. 1.2(a) -- sample data movement operations for SIC
Source statement
description
LDA
FIVE
Load constant 5 into reg. A
STA
ALPHA
Store in ALPHA
LDCH
CHARZ
Load char “Z” into reg. A
STCH C1
Store in character variable C1 …
RESW 1
One-word variable
WORD 5
One-word constant
BYTE
C”Z”
One-byte constant
RESB
One-byte variable

24. 2.2.3 SIC Programming
Fig. 1.2(b) -- sample data movement operations for SIC/XE
Source statement
description
LDA #5
Load value 5 into reg. A
STA
ALPHA
Store in ALPHA
LDCH
#90
Load ASCII code for “Z” into reg. A
STCH C1
Store in character variable C1 …
RESW 1
One-word variable
RESB

25. 2.2.3 SIC Programming
Fig. 1.3(a) -- sample arithmetic operations for SIC
Source statement
description
LDA
ALPHA
Load ALPHA into reg. A
ADD
INCR
Add the value of INCR
SUB
ONE
Subtract 1
STA
BETA
Store in BETA
GAMMA
Load GAMMA into reg. A
DELTA
Store in DELTA …

26. 2.2.3 SIC Programming Fig. 1.3(a) – cont’d Source statement
description
ONE
WORD 1
one-word constant
ALPHA
RESW
One-word variable
BETA
GAMMA
DELTA
INCR

27. 2.2.3 SIC Programming
Fig. 1.3(b) -- sample arithmetic operations for SIC/XE
Source statement
description
LDS
INCR
Load value of INCR into reg.S
LDA
ALPHA
Load ALPHA into reg. A
ADDR
S,A
Add the value of INCR
SUB #1
Subtract 1
STA
BETA
Store in BETA
GAMMA
DELTA …

28. 2.2.3 SIC Programming Fig. 1.3(b) – cont’d Source statement
description
ALPHA
RESW 1
One-word variable
BETA
GAMMA
DELTA
INCR

29. 2.3 Traditional Machines (CISC)
CISC– Complex Instruction Set Computers – about 200 or more instructions are provided
Characteristic of CISC
Have a large and complicated instruction set
Several different instruction formats
Many different addressing modes
Two real machines are exemplified
VAX series (PDP/11 & VAX)
Intel x86 family (x86 and Pentium Pro)

30. 2.4 RISC Machines Advantages of RISC computers
Faster and Less expensive processor development
Greater reliability
Faster instruction execution time

31. 2.4 RISC Machines Characteristics of RISC machines
Standard and fixed instruction length : 1 machine word in general
Single-cycle execution time for most instructions
Memory access is usually done by load and store instructions only
All instructions except for load and store are register-to-register type
A large number of register files are provided
The number of instructions, instruction formats, and addressing modes are relatively small

32. Questions and answers