1. Computer Architecture
Unit 1
Instruction Sets:
Characteristics
and Functions

2. Topics to covered Machine instructions characteristics
Types of operands
Intel x86 and ARM data types
Types of operations
Intel x86 and ARM operations types

3. What is an instruction set?
The collection of different instruction that the processor can execute is referred to as the instruction set. 2

4. Instruction Cycle State Diagram
Det the add of the operand
Perform op indicated in inst

5. Machine Instruction Characteristics
The operation of the processor is determine by the instruction it executes is know as m/c instruction or computer instruction
Different Machine instruction char.
1.Element of machine design
2.Instruction Representation
3.Instruction Types
4.Number of Address
5.Instruction set design

6. Elements of an Instruction
Operation code (Op code)
Do this (for ex : Add, Sub etc)
Source Operand reference
To this (for ex : Number of inputs )
Result Operand reference
Put the answer here
Next Instruction Reference
When you have done that, do this... 3

7. From where all the Operands come?
Source and Result can be in one of the four operands :
Main memory (or virtual memory or cache)
CPU register
Immediate
I/O device 4

8. Instruction Representation
Each instruction is represented by sequence of bits.
During execution , an instruction is read into instruction reg (IR) in the processor.
The processor must be able to extract data from the various fields to perform the required operation.
It is not possible to deal with the binary representation of m/c instr. So to solve this problem “Symbol representation” is introduced 5

9. Simple Instruction Format
The instruction is divided into various fields.
Fig : A Simple Instruction Format

10. Instruction Representation (continue.…)
Opcode are represented using abbreviation.
Common example are
ADD, SUB, MUL, DIV, LOAD, STOR
For example
ADD R,Y
It is represented as
X=X+Y

11. Instruction Types Consider X=X+Y
Let corresponding address of variable x and y location will be 513 and 514.
By using simple set of m/c instruction as follows :
1. R <- X
2. R + Y
3. R -> X

12. Instruction Types Data processing- Arithmetic and Logic inst.
Data storage -movement of data in or out of register or memory
Data movement - I/O
Program flow control- Test and Branch 6

13. Number of Addresses (a)
Two operand location and one result location
Operand 1, Operand 2, Result
a = b + c;
Temporary location “T” is used
Format is Not common
Needs very long words to hold everything 7

14. Y=(A-B)/(C+(D*E)) Instruction Comment SUB Y,A,B ;Y<-A-B
MPY T,D,F ;T<-D*E
ADD T,T,C ;T<-T+C
DIV Y,Y,T ;Y<-Y/T

15. Number of Addresses (b)
One address doubles as operand and result
SUB Y,B
MOVE instruction is used to move the data 8

16. Y=(A-B)/(C+(D*E)) Instruction Comment MOVE Y,A ;Y <- A
SUB Y,B ;Y <- Y-B
MOVE T,D ;T <- D
MPY T,E ;T <- T*E
ADD T,C ;T <- T+C
DIV Y,T ;Y <- Y/T

17. Number of Addresses (c)
Implicit second address
Usually a register (accumulator OR AC)
Common on early machines 9

18. Y=(A-B)/(C+(D*E)) Instruction Comment LOAD D ; AC <- D
MPY E ; AC <- AC * E
ADD C ; AC <- AC + C
STOR Y ; Y <- AC
LOAD A ; AC <- A
SUB B ; AC <- AC-B
DIV Y ; AC <- AC / Y

19. Number of Addresses (d)
0 (zero) addresses
All addresses implicit
Uses a stack
e.g. push a
push b
add
pop c
c = a + b 10

20. Y=(A-B)/(C+(D*E)) Instruction Comment PUSH A PUSH B SUBSTRACT PUSH C
PUSH D
PUSH E
MULTIPLY
ADD
DIVIDE
POP Y

21. How Many Addresses More addresses Fewer addresses
More complex instructions
More registers
Inter-register operations are quicker
Fewer instructions per program
Fewer addresses
Less complex (powerful?) instructions
More instructions per program
Faster fetch/execution of instructions 11

22. Types of Operand Addresses (Addressing Modes) Numbers Characters
Integer
floating point
Characters
American Standard code for information interchange(ASCII) etc.
Logical Data
Bits or flags
Boolean function (1-true,0-false) 14

23. Data types
Intel X86 Data Types
ARM Data Types

24. INTEL X86 Data Types X86 Processor Support Data Type Of 8 bit (Byte)
16 bit (word)
32 bit (double word)
64 bit (quad word)
Addressing is by 8 bit unit
A 32 bit double word is read at addresses divisible by 4 15

25. X86 Data Types 16

26. X86 data types are as follows:
Packed byte and packed byte integer
Packed word and packed word integer
Packed double-word and packed double-word integer
Packed quad-word and Packed quad-word integer.
Packed single-precision floating point and Packed double-precision floating point

27. Format of Data Types 17

28. What is ARM?
An ARM processor is one of a family of CPUs based on the RISC (reduced instruction set computer) architecture developed by Advanced RISC Machines (ARM).
ARM Processor Features Include:
Load/store architecture.
Enhanced power-saving design.
64 and 32-bit execution states for scalable high performance.

29. ARM Data Types
ARM Processor support data type of
8 bit
16 bit
32 bit

30. ARM Data-types The architecture support three alternative
1. Default case
2. Alignment checking
3. Unaligned Access

31. Types of Operation Data Transfer Arithmetic Logical Conversion I/O
System Control
Transfer of Control 18

32. Data Transfer Operation Name Move Store Load (Fetch) Exchange
Clear (Reset)
Set
Push
Pop 19

33. Arithmetic Add Subtract Multiply Divide Increment (a++)
Decrement (a--)
Negate (-a) 20

34. LOGICAL OPRATION NAME AND OR NOT XOR TEST COMPARE SET CONTROL VARIABLE
SHIFT
ROTATE

35. Shift and Rotate Operations

36. Conversion
Translate
It Translates value in a memory based on operation perform
Convert
Convert the content of the word from one from to another 22

37. Input / Output May be specific instructions
May be done using data movement instructions (memory mapped)
May be done by a separate controller (DMA) 23

38. Systems Control
System control instruction are those that can be execution only while the processor is in the certain privileged state. 24

39. Branch instruction
A branch instruction, also called a jump instruction, has as one of its operands the address of the next instruction to be executed
Two type of branches :
conditional branch
unconditional branch
There are four different conditional branch instructions:
BRP X Branch to location X if result is positive.
BRN X Branch to location X if result is negative.
BRZ X Branch to location X if result is zero.
BRO X Branch to location X if overflow occurs.

41. Skip Instructions
Another form of transfer-of-control instruction is the skip instruction.
The skip instruction includes an implied address
A typical example is the increment-and-skip-if-zero (ISZ) instruction.

42. Procedure call instruction

43. Processor Action On Various Types Of Operation
Data Transfer
Arithmetic
Logical
Conversion
I/O
System Control
Transfer of Control 25

44. X-86 Operation Data Movement Arithmetic Logical Control Transfer
String Operation
High Level Language Support
Flag Control
Segment Register
Protection
Cache Mgt.

45. X86 operation : 1. Data movement
PUSH
PUSH A
MOVSX
LEA
XLAT
IN/OUT

46. 2. Arithmetic
ADD
SUB
MUL
IDIV
IMUL

47. 3. Logical
AND
BTS
BSF
SHL/SHR
SAL/SAR
ROL/ROR
SETcc

48. 4. Control Transfer
JMP
CALL
JE/JZ
LOOPE/LOOPZ
INT/INTO

49. 5.String operation MOVS LODS 6. High level language support ENTER
LEAVE
BOUND

50. 7. Flag Control STC – set carry flag LAHF – Load AH register
8. Segment Register
LDS – Load pointer into DS
HLT – halt
LOCK – lock on memory
ESC – Escape
WAIT

51. 9. Protection SGDT – store global descriptor table
LSL – load segment limit
VERR/VERW – Verify segment for read/write
10. Cache Management
INVD – internal cache memory is removed
WB-INVD – memory is cleared after writing
INV LPG – invalidates a translation look aside buffer

52. CALL / ENTER and LEAVE/RETURN INSTRUCTION
MEMORY MANAGEMENT
STATUS FLAGE AND CONDITION CODES

53. STATUS FLAGE AND CONDITION CODES

55. Status Flags
The processor uses the status flag to reflect the result of an operation.
The status flags are located in the bits 0,2,4,6,7 and 11.
Carry Flag (CF)  CF=1 if there is a carry out from the most significant bit (MSB) on addition, or there is borrow into the MSB on subtraction. CF also contains the last bit of a shift or rotate instruction.
Parity flag (PF)  PF=1 if the low byte of a result has an even number of ones (Even parity).
Auxiliary carry Flag (AF)  AF=1 if there was a carry from or borrow to bits 0-3 in the AL register.
Zero Flag (ZF)  ZF=1 if the result is zero.
Sign Flag (SF)  SF=1 if the most significant bit of the result is 1. (i.e.) the result is negative.
Overflow Flag (OF)  OF=1, if the result is too large positive number, or is too small negative number to fit into the destination operand.

56. The control flags are used to enable or disable certain operations of the processor.
The control flags are located in the bits 8, 9, and 10.
Trap Flag (TF) If  TF=1,  then single-step interrupt will occur after the next instruction. Debugger programs such as DEBUG set the trap flag, so that we can step through the execution single step at a time to examine its effect on registers and memory.
Interrupt Flag (IF) Indicates that all the external interrupts such as keyboard entry are to be processed or ignored. IF=0 then inputs from the keyboard are ignored by the processor.
Direction Flag (DF) If set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented.  

57. ARM operation types Load And Store Instructions Branch Instructions
Data Processing Instructions
Multiply Instructions
Parallel Addition And Subtraction Instructions
Extend Instructions
Status Register

58. Condition codes of ARM
The ARM architecture defines four condition flags that are stored in the program status register:
---- N, Z, C, and V with meanings essentially the same as the S, Z, C, and V flags in the x86 architecture.

59. Two uses of condition flag
All instructions, not just branch instructions, include a condition code field, which means that virtually all instructions may be conditionally executed.
All data processing instructions (arithmetic, logical) include an S bit that signifies whether the instruction updates the condition flags.