Download presentation
Presentation is loading. Please wait.
1
M1.5 Foundation Tools Xilinx XC9500/XL CPLD
M1.5 Software/Fndtn
2
Agenda Program Manager Synthesis Implementation Fitting Report
Timing Report
3
M1.5 Software Foundation provides simple interface from start to finish Integrated Project and Design Manager Full version and revision control Design entry Schematic VHDL Verilog ABEL FSM
4
Project Manager
5
Version Control (proj mgr)
6
Project Manager Allows for top level view of project
Shows top level source Gives access to source hierarchy Push-button access to Design Entry tools Design Synthesis tools Design Implementation tools Download tools Simulation Tools
7
Project Manager Tabs give access to version and revision reports
error messages
8
Basic Steps to Programmed Logic
Start Project Manager Complete design entry Make certain that project contains top-level design Synthesize Simulate functional performance (suggested) Implement Simulate (Verify) timing and functionality (suggested) Program/Configure Device(s)
9
Basic Steps to Programmed Logic
Start by clicking “START” -> “Programs” -> “Xilinx Foundation”-> “Xilinx Foundation Project Manager” (or the Foundation icon) Enter design HDL Finite State Machine Editor schematic Make certain that project contains all design files “Project” -> “Add Source Files” Specify Top-Level Design
10
Basic Steps to Programmed Logic
Synthesize Simulate Functionality Implement
11
Basic Steps to Programmed Logic
Simulate / Verify Timing Performance Program/Download
12
Steps to Programmed Logic
Synthesize Design File Creates netlist from input file VHDL Verilog ABEL
13
Steps to Programmed Logic
14
Part Selector Choose device/family Run
15
Steps to Programmed Logic
Implement Netlist Choose performance criteria (speed vs density) Enable “Produce Configuration Data” to create filename.jed for programming device Process Netlist and Fit to Architecture (Run)
16
Implementation Revision Options Run
17
Options Implementation options
Target options (Produce Configuration Data for output file)
18
Implementation: Standard Options
Allow for quick selection Optimize for: speed density
19
Implementation: Flow Engine
20
Steps to Programmed Logic
Review fitter report file to verify fit and pin locations Here is an introduction to the reports
21
Reports Synthesis Implementation post-synthesis report optimized.chp
netlist logfile netlist.log Implementation translation report project.bld fitter report project.rpt timing report project.tim
22
Implementation Reports
Translation reports unused nets reports nets with no load or driver Fitter gives detailed information about the fitting and usage of CPLD device Timing gives detailed information about internal timing paths
23
Implementation Reports
Read report by selecting “Report Browser”
24
Implementation Reports
Yellow Sparkle indicates whether read
25
Design Example Sync DRAM controller
Project included on lab disk as sdram1 File included on lab disk as sdramctl.vhd Report and timing files included Netlist file included
26
Fitting Report -Resources
27
Fitting Report- Resources (cont)
28
Fitting Report- FB Global
29
Timing Report (Summary)
30
Steps to Programmed Logic
Program Device Connect download cable Invoke JTAG Programmer Establish Chain Program the device
31
JTAG Programmer
32
JTAG Programmer
33
Conclusion Foundation provides a simple and efficient method for taking a design from entry to programmed device. Synthesis allows for easy netlist generation. Implementation creates a file for programming the CPLD and provides in depth reports. JTAG Programmer provides a simple method for programming in system.
Similar presentations
© 2025 SlidePlayer.com. Inc.
All rights reserved.