Single Bit ALU 3 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d O

Single Bit ALU 3 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d O
3 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d O v e r f l o w c t i o n b .

CarryOut = ab + aCI + bCI a b CI + CarryOut

c0 a0 b0 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 2 gates c1 4 gates c2 c3 6 gates Ripple Carry c4 ci+1 = ai bi + ai ci + bi ci 8 gates 10 gates c5 c6 12 Gates

Carry Lookahead Adder ci is CarryIn i
c1 = a0 b0 + (a0+b0)c0

c1 = a0 b0 + (a0+b0)c0 c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] = a1b1+a1a0b0+a1a0c0+a1b0c0+b1a0b0+ b1a0c0+b1b0c0

c1 = a0 b0 + (a0+b0)c0 c2 = a1 b1 + (a1+b1)c1
c lah c2 c1 c1 = a0 b0 + (a0+b0)c0 c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] = a1b1+a1a0b0+a1a0c0+a1b0c0+b1a0b0+b1a0c0+b1b0c0 + c2

c1 = a0 b0 + (a0+b0)c0 c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] = a1b1+a1a0b0+a1a0c0+b1a0b0+b1a0c0+b1b0c0 One bit lookahead ci two gate delays from ci-2 for i even Reduces gate delays for 32 bits from 64 to 32

c1 = a0 b0 + (a0+b0)c0 c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] c2 =a1b1+a1a0b0+a1a0c0+a1b0c0+b1a0b0+b1a0c0+b1b0c0 One bit lookahead ci two gate delays from ci-2 for i even Reduces gate delays for 32 bits from 64 to 32 c3 = a2b2+(a2+b2)c2 c4 = a3b3+(a3+b3)c3 c4 = a3b3+(a3+b3) [a2b2+(a2+b2)c2] c4 =a3b3+a3a2b2+a3a2c2+a3b2c2+b3a2b2+b3a2c2+b3b2c2

c0 a0 b0 a1 b1 One Bit Lookahead a2 b2 a3 b3 c1 c2 a4 b4 a5 b5 c3 c4
c lah a2 b a3 b3 c1 c c2 c lah a4 b a5 b5 c3 c4 c lah c 6 Gates c5 c6

c1 = a0 b0 + (a0+b0)c0 c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] c3 = a2 b2 + (a2+b2)c2 = a2 b2 + (a2+b2){a1 b1+(a1+b1)[a0 b0+(a0+b0)c0]}

c1 = a0 b0 + (a0+b0)c0 c2 = a1 b1 + (a1+b1)c1 = a1 b1 + (a1+b1)[a0 b0 + (a0+b0)c0] c3 = a2 b2 + (a2+b2)c2 = a2 b2 + (a2+b2){a1 b1+(a1+b1)[a0 b0+(a0+b0)c0]} Note the patterns generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci if gi = 1, ci+1 = 1, if gi = 0 and pi = 1, ci+1 = ci

generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci c1 = g0+p0c0

generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci c1 = g0+p0c0 c2 = g1+p1g0+p1p0c0

generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci c1 = g0+p0c0 c2 = g1+p1g0+p1p0c0 c3 = g2+p2g1+p2p1g0+p2p1p0c0

generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci c1 = g0+p0c0 c2 = g1+p1g0+p1p0c0 c3 = g2+p2g1+p2p1g0+p2p1p0c0 c4 = g3+p3g2+p3p2g1+p3p2p1g0+p3p2p1p0c0

generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci c1 = g0+p0c0 c2 = g1+p1g0+p1p0c0 c3 = g2+p2g1+p2p1g0+p2p1p0c0 c4 = g3+p3g2+p3p2g1+p3p2p1g0+p3p2p1p0c0 Limited by Gate Fan-in contraints

ci+1 = gi + pi ci c1 = g0+p0c0 c2 = g1+p1g0+p1p0c0 c3 = g2+p2g1+p2p1g0+p2p1p0c0 c4 = g3+p3g2+p3p2g1+p3p2p1g0+p3p2p1p0c0 c5 = g4+p4c4 c6 = g5+p5g4+p5p4c4 c7 = g6+p6g5+p6p5g4+p6p5p4c4 c8 = g7+p7g6+p7p6g5+p7p6p5g4+p7p6p5p4c4 Each 4 bit stage has 2 gate delays per stage + 1 for g & p

Using Generate & Propagate
4 bit Carry Lookahead Using Generate & Propagate c0 a0,...,a3 b0,...,b3 generate gi = ai bi propagate pi = ai + bi ci+1 = gi + pi ci ALU s0,...s3 c4 a4,...,a7 b4,...,b7 g p ALU s4,...,s7 1 c8 g p a8,...,a11 b8,...,b11 ALU s8,...s11 2 c12 a12,...,a15 b12,...,b15 g p ALU s12,...,s15 3 c16

4 bit Carry Lookahead 2nd Level Lookahead c0 a0,...,a3 b0,...,b3 ALU
so,...s3 c4 a4,...,a7 b4,...,b7 g p ALU s4,...,s7 1 c8 g p a8,...,a11 b8,...,b11 ALU s8,...s11 2 c12 c8 a12,...,a15 b12,...,b15 g p G P ALU s12,...,s15 3 c16

G2 = g11+p11g10+p11p10g9+p11p10p9g8 P2 = p11p10p9p8 c12= G2 +P2c8 c8 g
a8,...,a11 b8,...,b11 ALU s8,...s11 2 c12 a12,...,a15 b12,...,b15 g p G P ALU s12,...,s15 3 c16

G2 = g11+p11g10+p11p10g9+p11p10p9g8 P2 = p11p10p9p8 c12= G2 +P2c8
c13=g12+p12G2+p12P2c8 c8 g p a8,...,a11 b8,...,b11 ALU s8,...s11 2 c12 a12,...,a15 b12,...,b15 g p G P ALU s12,...,s15 3 c16

c13=g12+p12G2+p12P2c8 c14=g13+p13g12+p13p12G2+p13p12P2c8 c8 g p a8,...,a11 b8,...,b11 ALU s8,...s11 2 c12 a12,...,a15 b12,...,b15 g p G P ALU s12,...,s15 3 c16

c13=g12+p12G2+p12P2c8 c14=g13+p13g12+p13p12G2+p13p12P2c8 c15=g14+p14g13+p14p13g12+p14p13p12G2 +p14p13p12P2c8 c8 g p a8,...,a11 b8,...,b11 ALU s8,...s11 2 c12 a12,...,a15 b12,...,b15 g p G P ALU s12,...,s15 3 c16

c13=g12+p12G2+p12P2c8 c14=g13+p13g12+p13p12G2+p13p12P2c8 c15=g14+p14g13+p14p13g12+p14p13p12G2 +p14p13p12P2c8 c16=g15+etc c8 g p a8,...,a11 b8,...,b11 ALU s8,...s11 2 c12 a12,...,a15 b12,...,b15 g p G P ALU s12,...,s15 3 c16

Logical Instructions shift left logical sll Shift left shamt bits and fill with 0’s sll $s1, $s2, 10 # $s1 = $s2 << 10 op rs rt rd shamt funct

Logical Instructions shift left logical sll Shift left shamt bits and fill with 0’s sll $s1, $s2, 10 # $s1 = $s2 << 10 op rs rt rd shamt funct shift right logical srl Shift right shamt bits and fill with 0’s srl $t0, $s0, 16 # $t0 = $s0 >> 16

Logical Instructions logical AND and bit- by-bit logical AND and $s0, $s1, $s2 # $s0 = $s1 & $s2 op rs rt rd shamt funct

Logical Instructions logical AND and bit- by-bit logical AND and $s0, $s1, $s2 # $s0 = $s1 & $s2 op rs rt rd shamt funct logical AND immediate andi $t0, $t1, 7 # $t0 = $t1 & ( )

Logical Instructions logical AND and bit- by-bit logical AND and $s0, $s1, $s2 # $s0 = $s1 & $s2 op rs rt rd shamt funct logical AND immediate andi $t0, $t1, 7 # $t0 = $t1 & ( ) logical OR or $s1, $t1, $s2 # $s1 = $t1 | $s2 logical OR immediate ori $t1, $s1, 8 # $t1 = $s1 | ( )

Multiplication - Positive numbers
Example: Multiplicand x Multiplier

Example: Multiplicand x Multiplier 0010

Example: Multiplicand x Multiplier 0010 0000

Example: Multiplicand x Multiplier 0010 0000 Product

Example: Multiplicand n bits x Multiplier m bits add shift left and add shift left and do nothing shift left and add Product n+m bits

Multiplicand 00000010 Multiplier 1011 Control Test Product 00000000
Shift left Multiplier 1011 8 bit ALU Control Test Shift right Product 1. 1 implies add

Shift left Multiplier 1011 8 bit ALU Shift right Control Test Product 1. 1 implies add 2. Shift

Shift left Multiplier 1011 8 bit ALU Shift right Control Test Product 1. 1 implies add

Shift left Multiplier 1011 8 bit ALU Shift right Control Test Product 1 implies add Shift

Shift left Multiplier 1011 8 bit ALU Shift right Control Test Product 0 no op

Shift left Multiplier 1011 8 bit ALU Shift right Control Test Product 0 no op Shift

Shift left Multiplier 1011 8 bit ALU Shift right Control Test Product 1 implies add

Shift left Multiplier 1011 8 bit ALU Shift right Control Test Product 1 implies add Shift

Shift left Multiplier 1011 8 bit ALU Shift right Control Test Product

Note: Half of the bits always 0 Multiplicand 00100000 Multiplier 1011
Shift left Multiplier 1011 8 bit ALU Shift right Control Test Product

Multiplication - Positive numbers – Shift Sum
Example: Multiplicand x Multiplier 0010

Multiplication - Positive numbers – Shift Sum Example: Multiplicand x Multiplier 0010 00110

4 bit ALU Control Test Shift right Product 1. 1 implies add Shift right

4 bit ALU Control Test Shift right Product 1 implies add Shift Shift right

4 bit ALU Control Test Shift right Product 1 implies add Shift right

4 bit ALU Control Test Shift right Product 0 no op Shift Shift right

4 bit ALU Control Test Shift right Product 1 implies add Shift right

4 bit ALU Control Test Shift right Product Shift right

Note: Product uses space as Multiplier decreases
Multiplicand 0010 Multiplier 1011 4 bit ALU Control Test Shift right Product Shift right Note: Product uses space as Multiplier decreases

Multiplicand 0010 Control Test Product 00001011 1. 1 implies add
4 bit ALU Control Test Product 1. 1 implies add Shift right Multiplier (1011)

Multiplicand 0010 Control Test Product 00101011 1 implies add Shift
4 bit ALU Control Test Product 1 implies add Shift Shift right Multiplier (1011) Multiplier

Multiplicand 0010 Control Test Product 00010101 1 implies add
4 bit ALU Control Test Product 1 implies add Shift right Multiplier (1011) Multiplier

Multiplicand 0010 Control Test Product 00011010 0 no op Shift
4 bit ALU Control Test Product 0 no op Shift Shift right Multiplier (1011) Multiplier

Multiplicand 0010 Control Test Product 00001101 1 implies add
4 bit ALU Control Test Product 1 implies add Shift right Multiplier (1011) Multiplier

Multiplicand 0010 Control Test Product 00010110 Multiplier (1011)
4 bit ALU Control Test Product Shift right Multiplier (1011) Multiplier

MIPS Instructions for Multiply and Divide
Hi,Lo are two 32 bit registers for Product and Remainder multiply mult $s1, $s2 # Hi,Lo = $s1 x $s2 For signed numbers, 1. determine the sign of the product 2. convert to positive representation 3. multiply 4. determine the sign and convert to 2’s complement if needed

Hi,Lo are two 32 bit registers for Product and Remainder multiply mult $s1, $s2 # Hi,Lo = $s1 x $s2 multiply unsigned multu $s1, $s2 # Hi,Lo = $s1 x $s2 ( unsigned) MIPS ignores overflow, so it is up to the software. What is the overflow condition for mult $s1, $s2?

Hi,Lo are two 32 bit registers for Product and Remainder multiply mult $s1, $s2 # Hi,Lo = $s1 x $s2 multiply unsigned multu $s1, $s2 # Hi,Lo = $s1 x $s2 ( unsigned) MIPS ignores overflow, so it is up to the software. What is the overflow condition for mult $s1, $s2? Hi must be zero or the sign extension of Lo.

Hi,Lo are two 32 bit registers for Product and Remainder multiply mult $s1, $s2 # Hi,Lo = $s1 x $s2 multiply unsigned multu $s1, $s2 # Hi,Lo = $s1 x $s2 ( unsigned) move from Hi mfhi $s3 # $s3 = Hi

Hi,Lo are two 32 bit registers for Product and Remainder multiply mult $s1, $s2 # Hi,Lo = $s1 x $s2 multiply unsigned multu $s1, $s2 # Hi,Lo = $s1 x $s2 ( unsigned) move from Hi mfhi $s3 # $s3 = Hi move from Lo mflo $s3 # $s3 = Lo

Single Bit ALU 3 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d O

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Single Bit ALU 3 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d O

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Presentation on theme: "Single Bit ALU 3 R e s u l t O p r a i o n 1 C y I B v b 2 L S f w d O"— Presentation transcript:

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