1. Prof. Haung, Jung-Tang NTUTL
微機電技術(Microelectromechanical) (I)
CMOS 製程簡介
Prof. Haung, Jung-Tang
NTUTL

2. Photolithography
Conceptual example of the use of photolithography to form a pn junction diode.
Chap.5 製程簡介

3. Fabrication Steps for NMOS Transistor
(a).Patterning SiO2 Layer
(b).Gate Oxidation
(c).Patterning polysilicon
(d).Implant or diffusion
(e).Contact Cuts
(f).Patterning of Aluminum Layer
Chap.5 製程簡介

4. CMOS Process and Layout Drawing Conventions (公約或協定)
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5. Basic N-well CMOS Process (I)
PMOS is on N-well.
(b)
SiN
SiO2
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6. Basic N-well CMOS Process (II)
Preventing conduction between unrelated transistor source/drains.
LOCOS (LOcal Oxidation Of Silicon) results in an active area that is smaller than patterned.
Thick field oxide is grown where the SiN layer is absent.
(d)
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7. Basic N-well CMOS Process (III)
The “poly” gate regions lead to “self-aligned” source-drain regions.
(e)
A thin-oxide area exposed by the n-plus mask will become an n+ diffusion area.
(f)
An ohmic contact is no junction. Current can flow in both directions in this contact. n+
NMOS
Ohmic contact
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8. Basic N-well CMOS Process (IV)
LDD (Lightly Doped Drain structure)
(a): The following figure consists of a shallow n-LDD implant that covers the
source/drain region where there is no poly.
(b): A spacer oxide is then grown over the polysilicon gate.
(C): Put heavier implant to source/drain region where there is no poly.
LDD results a structure that is more resistant to hot-electron effects.
(g)
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9. Basic N-well CMOS Process (V)
(h)
The LDD (Lightly Dopped Drain structure) step is not necessarily done for p-transistors because their hot-carrier is much less than that of n-transistors.
NMOS
PMOS
The drawn length dimension of p-transistors might be larger than drawn length of the n-transistors.
(i)
SiO2
Metal
(j)
Chap.5 製程簡介

10. Cross Section of a CMOS Inverter
(a): Inverter schematic
(c): Cross-section in N-well
SiO2
Drain
Gate
Source
(b): Layout
(d): Physical structure
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11. Substrate and Well contacts in N-well Ohmic contact in N-well
PMOS
NMOS
Ohmic contact in P-sub.
Ohmic contact in N-well
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12. Twin-Tub (well) Process
Epitaxial layer is used to against latchup.
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13. Structure of BJT Transistor (1)
Triple-diffused transistor and resulting impurity profile.
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14. Structure of BJT Transistor (2)
Typical impurity concentration
for a monolithic npn transistor
in a high-voltage, deep-diffused
process.
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15. Structure of BJT Transistor (3)
Integrated-circuit npn BJTs. The layout is made as shown.
Chap.5 製程簡介

16. Structure of BJT Transistor (4)
Lateral npn BJTs fabricated in a high-voltage process.
Chap.5 製程簡介

17. Structure of BJT Transistor (5)
Substrate pnp structure in a high-voltage, thick-epi process.
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18. Physical Structure
E-NMOS Type
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19. Bias Gate Voltage of E-NMOS
The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.
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20. Applying a Small VDS
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21. Operation as VDS is Increased
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22. Drain Current versus Drain-source Voltage
Saturation Region
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23. Active Devices in MOS Integrated Circuits (1)
Layout of an n-channel silicon-gate MOS transistor.
Chap.5 製程簡介

24. Active Devices in MOS Integrated Circuits (2)
NMOS device characteristics.
Drain-current:
Function of the square root of gate-
source voltage in the active region.
Chap.5 製程簡介

25. Resistors in MOS Technology (1)
Diffused Resistors (n+ or p+): using to
form source or drain.
Well resistors: A sheet resistance of 10k/.
Polysilicon Resistors:
(1). Gate material. Nominal sheet
resistance = 20/ ~ 80/.
(2). Large variation around the nominal
value due to process variation.
MOS Device as Resistors:
(1). Biased in triode region.
Triode Region:
Active Region:
where
(2). Resistance:
(3). This resistance can be much higher than polysilicon and diffused
resistor.
Chap.5 製程簡介

26. Resistors in MOS Technology (2)
Operating regions of npn bipolar and n-channel MOS transistors.
P34, Fig. 1.31
Symmetry
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27. Capacitors in MOS Technology (1)
Poly-poly Capacitors
1. Parasitic capacitance:
(1).Bottom plate is substrate or well: 10%~30%。
(2).Top plate is interconnect metallization: 5~50fF.
2. Temperature variations < 50ppm/℃.
MOS Transistors as Capacitors
1. Biased in the triode region.
(1).Top plate: gate.
(2).Bottom plate: source, drain, and channel.
(3).Higher capacitance.
2. Drawback:
(1).A large amount of surface potential variation occurs with applied voltage.
(2).High voltage coefficient (ppm/V).
Chap.5 製程簡介

28. Capacitors in MOS Technology (2)
Other vertical Capacitor Structures
1.Extra masking:
(1).A thin-oxide layer between the polysilicon and the interconnect metallization.
(2).A diffused layer exists under the polysilicon in a thin-oxide area.
2. Standard process: 1 polysilicon + 2 metal.
(1).Top plate : ploy + matal 1.
(2).Bottom plate : metal2.
(3).Drawback: small capacitance and large area.
Lateral Capacitor Structures
(metal layer with space)
1.Capacitance = (width×thickness×
dielectric_constant)/space
Reducing space can both save the
area and increase capacitance.
2. Lateral + Vertical capacitances
This concept can be extended to
additional pieces in each layer
and additional layers.
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29. CMOS Technology
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30. BiCMOS Technology
Typical device: high-frequency(fT=50GHz), low-voltage, and
oxide-isolated BiCMOS process.
Advantages:
Local oxide isolation: Reducing the Collector-Substrate parasitic capacitance.
Dense-packed.
High current-driving capacibility of BJT.
Taking the characteristics of both types of N- and P-MOS.
Chap.5 製程簡介