1. Preliminary
Computer Organization and Design 3rd edition, Designers Guide to VHDL. 1

2. Computer Organization and Design
This book and the slightly more advanced Computer Architecture a Quantitative Approach are the dominant computer architecture text books.
Too big.
Chapter 1 – Read
Chapter 2-7 – will be covered in detail skipping some material.
Chapters 8-9 – Will depend on time.
Supplement with additional material. 2

3. Introduction
We will learn not just how computers work, but gain an understanding into how and why computers evolved into the current generation.
Computer have undergone rapid changes.
Increasing performance
Decreasing cost 3

4. History Computers did not really begin until World War II.
The widespread use of microprocessors began about 35 years ago.
Personal computers were not taken seriously until the introduction of the IBM PC in 1981. 4

5. Computers have resulted in the information revolution.
Agricultural revolution.
Several Thousand years.
Industrial revolution.
Several Hundred years.
Information revolution.
A couple of decades. 5

6. My History
I started at NASA in 1963 and worked in the computer division.
At that time computers were very expensive and very large.
Programs were written on punched cards (one line per card) and fed into the computer.
The state-of-the-art super computer that I worked with was capable of executing one million instructions per second, it cost several million dollars, and occupied the major portion of a large building. 6

7. My History continued
In the 60’s I did early work in interactive computing techniques.
Forerunner of what we do today, but not practical when it required a dedicated super computer connected to a display console.
In 1974 I completed my PhD and started working with microprocessors. 7

8. Moore’s Law
One of the founders of Intel, Dr. Gordon Moore, observed in 1965 that the number of transistors in an IC was doubling every year. He predicted that this would continue for a couple of decades and then slow to doubling every 18 months.
This prediction has proved remarkably accurate. So much so that it has come to be expected, and Moore’s prediction has become known as Moore’s law.
It is worth noting that since Moore made his prediction the consensus at any time has been that it would last for only about ten more years.
Economics not technology may be what actually stops Moore’s law. 8

9. 9

10. 10

11. 11

12. 12

13. 13

14. Single instruction stream – single data stream14

15. Multiple instruction stream – multiple data stream.15

16. Single instruction stream – single data stream16

17. 17

18. Definitions
Efficiency is the measurement of how close we come to achieving ideal speed up. 18

19. 19

20. Assumptions All operations take one unit of time.
All instructions and data are available when needed.
i.e. We don’t have to wait for memory or communication.
This is naïve and completely unrealistic, but can be used to teach some fundamental truths. 20

21. Conventional uniprocessor (SISD)
A1*B1
A2*B2
A3*B3
A4*B4 …
An*Bn 1 2 3 4 5 6 21

22. Multiprocessor MIMD (unlimited processors) SIMD – same results.
A1*B1
A2*B2
A3*B3
A4*B4 …
An*Bn 1 2 3 4 5 6 22

23. Multifunction computer (2 * units)
A1*B1
A2*B2
A3*B3
A4*B4 …
An*Bn 1 2 3 4 5 6 23

24. SISD – single processor T A1 A2 A3 A4 A5 An 1 2 3 4 5 624

25. MIMD or SIMD – with unlimited processors T A1 A2 A3 A4 A5 An 1 2 3 4 5 6 25

26. Algorithm can effect speedup. SISD
A (B C D + E)
A B C D +A E 1 2 3 4 5 6 26

27. Algorithm can effect speedup. MIMD
A (B C D + E)
A B C D +A E 1 2 3 4 5 6 27

28. A0 + A1*X + A2*X*X + A3*X*X*X + A4*X*X*X*X
SISD Method A T
A0 + A1*X + A2*X*X + A3*X*X*X + A4*X*X*X*X 1 2 3 4 5 6 7 8 9 10 11 28

29. A0 + A1*X + A2*X*X + A3*X*X*X + A4*X*X*X*X
SISD Method B T
A0 + A1*X + A2*X*X + A3*X*X*X + A4*X*X*X*X 1 2 3 4 5 6 7 8 9 10 11 29

30. A0 + X ( A1 +X ( A2 + X ( A3 + X ( A4 + …))))
SISD Method C T
A0 + X ( A1 +X ( A2 + X ( A3 + X ( A4 + …)))) 1 2 3 4 5 6 7 8 9 30

31. A0 + X ( A1 +X ( A2 + X ( A3 + X ( A4 + …))))
MIMD unlimited processors T
A0 + X ( A1 +X ( A2 + X ( A3 + X ( A4 + …)))) 1 2 3 4 5 6 7 8 9 31

32. A0 + A1*X + A2*X*X + A3*X*X*X + A4*X*X*X*X
MIMD unlimited processors T
A0 + A1*X + A2*X*X + A3*X*X*X + A4*X*X*X*X 1 2 3 4 5 6 7 8 9 32

33. A0 + A1*X + A2*X*X + A3*X*X*X + A4*X*X*X*X
SIMD unlimited processors T
A0 + A1*X + A2*X*X + A3*X*X*X + A4*X*X*X*X 1 2 3 4 5 6 7 8 9 33

34. Using an MIMD machine with unlimited processors, the time to compute
is given by
Where,
And,
for i > 2
For example when N = 9,
For N = 3000
T(3000)=23 34

35. Compute
using a SISD computer with a add-multiply arithmetic unit.
T(4) = 4 35

36. Pipeline examples 36

37. 37

38. 38

39. 39

40. 40

41. 41

42. Using a four segment pipeline with the restriction that the pipeline must empty before a new type (add, multiply, etc.) of operation can begin.
T4(4) = 16 segment times. 42

43. Using a four segment pipeline which does not require that the pipeline empty before a new type of operation can begin.
T4(4)=15 segment times. 43

44. EGRE 426 Fall 09 Handout 02

45. Pipeline examples continued from last class.

50. Using a four segment pipeline with the restriction that the pipeline must empty before a new type (add, multiply, etc.) of operation can begin.
T4(4) = 16 segment times.

51. Using a four segment pipeline which does not require that the pipeline empty before a new type of operation can begin.
T4(4)=15 segment times.

52. Chapter 2 The Mips processor
In this class we will focus on the Mips processor.
The Mips processor is an example of a reduced instruction set computer (RISC).
Hennessy and Patterson were early advocates of RISC architecture and were responsible for much of the early development of RISC concepts.
Hennessy left Stanford to found MIPS Computer Systems.
The first commercial Mips processor was introduced in
The Mips is used in a number of embedded systems including game consoles.
We will concentrate on an older 32 bit version of the Mips.
64 bit SIMD versions of Mips processors are available.
The impact of the Mips has been significantly reduced by the prevalence of the Intel X86 processors (CISC).

53. Instructions: Language of the Machine
We’ll be working with the MIPS instruction set architecture
similar to other architectures developed since the 1980's
RISC architecture
Almost 100 million MIPS processors manufactured in 2002
used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, …

54. MIPS arithmetic comment All instructions have 3 operands
Operand order is fixed (destination first) Example: C code: a = b + c MIPS ‘code’: add a, b, c # a  b + c (we’ll talk about registers in a bit) “The natural number of operands for an operation like addition is three…requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple”
However, note that two operands are typical on most computers
Add a, b # a  a + b
comment

55. MIPS arithmetic Design Principle: simplicity favors regularity.
Of course this complicates some things C code: a = b + c + d; MIPS code: add a, b, c add a, a, d
On the Mips operands must be registers, only 32 registers provided
Each register contains 32 bits
Design Principle: smaller is faster Why?

56. Registers vs. Memory
Arithmetic instructions operands must be registers, — only 32 registers provided
Compiler associates variables with registers
What about programs with lots of variables?
Use memory
Processor
I/O
Control
Datapath
Memory
Input
Output

57. Memory Organization
Viewed as a large, single-dimension array, with an address.
A memory address is an index into the array
"Byte addressing" means that the index points to a byte of memory.
Addresses Bytes
A 32 bit word consists of 4 bytes aligned as shown below. The address of the word points to the most significant byte of the word (Big endian).
8 bits of data 1
8 bits of data 2
8 bits of data 3
8 bits of data 4
8 bits of data 5
8 bits of data 6
8 bits of data
...

58. Memory Organization
Byte addressing is used, but most data items use "words"
For MIPS, a word is 32 bits or 4 bytes.
232 bytes with byte addresses from 0 to
230 words with byte addresses 0, 4, 8,
Words are aligned i.e., what are the least 2 significant bits of a word address?
Registers hold 32 bits of data
32 bits of data 4
32 bits of data 8
32 bits of data 12
32 bits of data
...

59. add $4, $5, $9
Assembler also recognizes
add $a0, $a1, $t1

60. Instructions Why 32? Load and store instructions
Example: C code: A[12] = h + A[8]; MIPS code: lw $t0, 32($s3) # $t0  M($s3+32) add $t0, $s2, $t0 # $t0  $s2 + $t0 sw $t0, 48($s3) # ?
Can refer to registers by name (e.g., $s2, $t2) instead of number
Store word has destination last
Remember arithmetic operands are registers, not memory! Can’t write: add 48($s3), $s2, 32($s3)
Why 32?

69. Our First Example Can we figure out the code? $5  k $?  v[]
swap(int v[], int k);
{ int temp;
temp = v[k]
v[k] = v[k+1];
v[k+1] = temp; }
Can we figure out the code?
swap:
muli $2, $5, 4
add $2, $4, $2
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
jr $31

70. So far we’ve learned:
MIPS — loading words but addressing bytes — arithmetic on registers only
Instruction Meaning add $s1, $s2, $s3 $s1 = $s2 + $s3 sub $s1, $s2, $s3 $s1 = $s2 – $s3 lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1

71. Machine Language
Instructions, like registers and words of data, are also 32 bits long
Example: add $t1, $s1, $s2
registers have numbers, $t1=9, $s1=17, $s2=18
Instruction Format: op rs rt rd shamt funct Can you guess what the field names stand for? See Page 63
Board work: Binary Numbers

72. Machine Language Consider the load-word and store-word instructions,
What would the regularity principle have us do?
New principle: Good design demands a compromise
Introduce a new type of instruction format
I-type for data transfer instructions
other format was R-type for register
Example: lw $t0, 32($s2) op rs rt 16 bit number
Where's the compromise?
What size offset would programmer like? Why is it only 16 bits?
Why not get rid of rs field and make offset 6 bits bigger?

73. Stored Program Concept
Instructions are bits
Programs are stored in memory — to be read or written just like data
Fetch & Execute Cycle
Instructions are fetched and put into a special register
Bits in the register "control" the subsequent actions
Fetch the “next” instruction and continue
Processor
Memory
memory for data, programs,
compilers, editors, etc.

74. Control Decision making instructions
alter the control flow,
i.e., change the "next" instruction to be executed
MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label
Example: if (i==j) h = i + j; bne $s0, $s1, Label add $s3, $s0, $s1 Label: ....

75. Control MIPS unconditional branch instructions: j label
Example: if (i!=j) beq $s4, $s5, Lab h=i+j; add $s3, $s4, $s5 else j Lab h=i-j; Lab1: sub $s3, $s4, $s Lab2: ...

78. So far: op rs rt rd shamt funct R I op rs rt 16 bit address J
Instruction Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 – $s3 lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1 bne $s4,$s5,L Next instr. is at Label if $s4 ≠ $s5 beq $s4,$s5,L Next instr. is at Label if $s4 = $s5 j Label Next instr. is at Label
Formats: R I J
op rs rt rd shamt funct
op rs rt 16 bit address
op bit address

79. Control Flow We have: beq, bne, what about Branch-if-less- than?
New instruction: if $s1 < $s2 then $t0 = 1 slt $t0, $s1, $s2 else $t0 = 0
Board work: Binary Numbers

80. Policy of Use Conventions
Register 1 ($at) reserved for assembler, for operating system

81. Constants
Small constants are used quite frequently (50% of operands) e.g., A = A + 5; B = B + 1; C = C - 18;
Solutions? Why not?
put 'typical constants' in memory and load them.
create hard-wired registers (like $zero) for constants like one.
MIPS Instructions: addi $29, $29, 4 slti $8, $18, andi $29, $29, 6 ori $29, $29, 4
Design Principle: Make the common case fast. Which format?

82. How about larger constants?
We'd like to be able to load a 32 bit constant into a register
Must use two instructions, new "load upper immediate" instruction lui $t0,
Then must get the lower order bits right, i.e.,
ori $t0, $t0,
filled with zeros
ori

83. Assembly Language vs. Machine Language
Assembly provides convenient symbolic representation
much easier than writing down numbers
e.g., destination first
Machine language is the underlying reality
e.g., destination is no longer first
Assembly can provide 'pseudoinstructions'
e.g., “move $t0, $t1” exists only in Assembly
would be implemented using “add $t0,$t1,$zero”
When considering performance you should count real instructions

84. Overview of MIPS simple instructions all 32 bits wide
very structured, no unnecessary baggage
only three instruction formats
rely on compiler to achieve performance
help compiler where we can R I J
op rs rt rd shamt funct
op rs rt 16 bit address
op bit address

85. Addresses in Branches and Jumps
Instructions:
bne $t4,$t5,Label Next instruction is at Label if $t4  $t5
beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5
j Label Next instruction is at Label
Formats:
Addresses are not 32 bits — How do we handle this with load and store instructions?
op rs rt 16 bit address I J
op bit address

86. Addresses in Branches op rs rt 16 bit address I Instructions:
bne $t4,$t5,Label Next instruction is at Label if $t4≠$t5
beq $t4,$t5,Label Next instruction is at Label if $t4=$t5
Formats:
Could specify a register (like lw and sw) and add it to address
use Instruction Address Register (PC = program counter)
most branches are local (principle of locality)
Jump instructions just use high order bits of PC
address boundaries of 256 MB
op rs rt 16 bit address I

87. Page 57

88. To summarize:

90. Alternative Architectures
Design alternative:
provide more powerful operations
goal is to reduce number of instructions executed
danger is a slower cycle time and/or a higher CPI
Let’s look (briefly) at IA-32
“The path toward operation complexity is thus fraught with peril. To avoid these problems, designers have moved toward simpler instructions”

91. IA - 32
1978: The Intel 8086 is announced (16 bit architecture)
1980: The 8087 floating point coprocessor is added
1982: The increases address space to 24 bits, +instructions
1985: The extends to 32 bits, new addressing modes
: The 80486, Pentium, Pentium Pro add a few instructions (mostly designed for higher performance)
1997: 57 new “MMX” instructions are added, Pentium II
1999: The Pentium III added another 70 instructions (SSE)
2001: Another 144 instructions (SSE2)
2003: AMD extends the architecture to increase address space to 64 bits, widens all registers to 64 bits and other changes (AMD64)
2004: Intel capitulates and embraces AMD64 (calls it EM64T) and adds more media extensions
“This history illustrates the impact of the “golden handcuffs” of compatibility “adding new features as someone might add clothing to a packed bag” “an architecture that is difficult to explain and impossible to love”

92. IA-32 Overview Complexity: Saving grace:
Instructions from 1 to 17 bytes long
one operand must act as both a source and destination
one operand can come from memory
complex addressing modes e.g., “base or scaled index with 8 or 32 bit displacement”
Saving grace:
the most frequently used instructions are not too difficult to build
compilers avoid the portions of the architecture that are slow
“what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective”

93. IA-32 Registers and Data Addressing
Registers in the 32-bit subset that originated with 80386

94. IA-32 Register Restrictions
Registers are not “general purpose” – note the restrictions below

95. IA-32 Typical Instructions
Four major types of integer instructions:
Data movement including move, push, pop
Arithmetic and logical (destination register or memory)
Control flow (use of condition codes / flags )
String instructions, including string move and string compare

97. ADC AX,[SI+BP-2]

98. IA-32 instruction Formats
Typical formats: (notice the different lengths)

99. Summary Instruction complexity is only one variable Design Principles:
lower instruction count vs. higher CPI / lower clock rate
Design Principles:
simplicity favors regularity
smaller is faster
good design demands compromise
make the common case fast
Instruction set architecture
a very important abstraction indeed!

100. Concluding Remarks
Evolution vs. Revolution “More often the expense of innovation comes from being too disruptive to computer users”
“Acceptance of hardware ideas requires acceptance by software people; therefore hardware people should learn about software. And if software people want good machines, they must learn more about hardware to be able to communicate with and thereby influence hardware engineers.”