1. Large area short strip arrays
Goal is to use a thin film technology “hybrid”
Option-i: Silicon hybrid (Interposer)
Option-ii: Post processing on the silicon sensor
Option-iii: Replace wire-bonding with flip-chip (2nd phase)
Thin film technology

2. The long-term vision ABC-N 256Ch (WB) Wire bonding to integrated fanin
digital section
Power, clock, command, data, etc.
ABC-N 256Ch (WB)
Amplifier pitch : 50 mm
Wire-bonding pitch: 80 mm
ABC-N 256Ch (FC)
Amplifier pitch: 50 mm
Bonding pitch: 300 mm
Silicon sensor
ASIC
Flip chip
Wire bonding
to integrated
fanin
Silicon interposer
Strips

3. Progress report - June/July
Review of material estimates for different technologies
Interaction with companies (A, I, S)
Visit to I (Marc)
2nd visit to A (Jeff, Lars, Marc)
Visit to S (Bob Stevens, CMF)
Split project into phases
RD on electrical parameters for sensor post processing
Prototyping of a silicon interposer
Post processed hybrid – subject to success with a) and b)
Flip chip – on hold
Integrated silicon cooling – on hold
Started on electrical design of hybrid (interposer)
Based on US 4-chip deign (currently working at RAL)
Need expert feedback and link into Liverpool work
Will invited Wuppertal to RAL to learn more about their post-processed pixel module
Investigated Microflex interconnection
Updated (more realistic?) schedule

4. Material Estimates (Marc)
Compared
Ceramic (BeO) based on Carl’s hybrid
Copper-Kapton based on extrapolation from Liverpool
A silicon hybrid (= Interposer) using thin-film technology
Post processing on sensor
Disclaimer: Many assumptions
ASIC size
Hybrid area
Metal layer thickness
CC bridge, thickness
Number of passives (e.g. for decoupling)
Thermal heat spreader area…
All radiation length estimates are normalized to sensor area

5. Material comparisons overview
(no base board, no pigtail, no MCC, no SP, see below) SLHC BeO: % R.L. SLHC Copper-Kapton: % R.L. (main uncertainty is thickness of CC bridge) SLHC post-processing: % R.L. SLHC silicon interposer: 1-1.2% R.L. SCT barrel module: % R.L. (Hybrid: 0.36%; Sensor: 0.61%, Baseboard/TPG: 0.19%)

6. Material comparisons details (simplified)
This is a condensed version of much more detailed info by Tim, Nobu, Carl and Marc

7. Preliminary conclusions on material
For short strips – the Hybrid material will exceed silicon sensor contribution for copper-Kapton technology despite reductions (double row, small size, no fan-outs)
Reduce ASIC length for the 0.13 m ABCD-Next version
Thin ASICs 0.3 mm
Eliminate fan-ins
With thin-film hybrids could reduce hybrid material by factor of 2-4.
~4: for thick CC bridge compared to post-processing
~2: for thin or no CC bridge compared to silicon interposer

8. Silicon interposer design & layouts
Obtain processing parameters and design rules
Design strategy
1) First design a clone of LBNL 4-chip hybrid
2) Test structures to characterise/evaluate:
Transmission lines
Surface mount procedure (glue, solder, wire-bonding…)
Microflex connection
Mechanical deformation for a 100mm wide object
3) Variation with surface area reduced by:
Move connector to the side. Possibly remove
Narrow the traces and move underneath ASIC
4) Serial powering variant

9. Processing parameters
Info from the 3 companies I, A and CMF are reasonably consistent
Substrate
I: 0.6mm, standard high resistivity silicon
A: 4’’ for post-processing on available sensors is OK
6’’ x ?mmfor silicon interposer (for cost reasons and to look at mechanical issues)
Dielectric: BCB (cyclotene); thickness 5-15 m
Will get more info on break-through voltages
Metal:
1-5 m Cu (issues are sputtering time and aspect ratios)
Minimum trace gap and width: m
Electromigration: Max. current density <10mA/ um width of copper at 1 m
Surface finish:
nickel/gold for aluminium wedge bonding or
nickel/palladium/gold for wedge bonding and soldering
Via diameter: determined by minimum trace width + ~450 opening angle
Number of layers:
A: 4 at 50 m width (additional layers without art-work should be OK)
I: “the less the better”

10. Electrical design issues
Geometry & layer thickness of thin-film MCMs require changes in design.
Issues are:
Transmission line impedance (impedances are lower in thin-film; pixel group achieved 50 Ws rather than the usual ~70 Ws with low cross talk)
Capacitances. Large capacitances because of thin dielectric help with decoupling but will increase total strip capacitance
Area and thickness of power and ground planes
Why don’t Pixel detectors have ground/power planes? If this is due to much reduced stray capacitances, short strips might make life easier!
High voltage routing and decoupling for detector bias
Attention to Guard ring and silicon edge if silicon extended

11. Simulation for silicon interposer
What we have to do before fabrication:
Simulate change of strip capacitance due to additional metal layers
Simulate impedance and cross talk for different transmission line geometries
Understand ground and shielding plane requirements and relation to ASIC design
Layout of simple test structures for sensor wafers (1-2 metal layers initially)
Layout of electrically functional silicon interposer
(3-4 metal layers)

12. Design and layout of silicon interposer
Install and gain experience with Cadence Allegro PCB design suite
Using existing functioning thick film hybrid layout
Import dxf layout and convert to copper layers
Combine copper layers to produce related layers thus producing via and dielectric layers
Reverse engineer design to create schematics
Produce GDSII output format for mask plate manufacture
Reproduce the design layout onto silicon substrate using MCM-D technology
Manipulate original design to reduce device width
Output design in GDSII format and combine on multi-design layout
Incorporate “Microflex” technology for connection to copper/kapton flex
Re-design layout for side entry connection and combine on multi-design layout

13. 3rd dielectric BCB (FD3) / via fill (FV3)
SMD Solder (FC4b)
Wirebond + fanin Au (FC4a)
3rd dielectric BCB (FD3) / via fill (FV3)
Gnd/trace2 Cu (FC3)
2nd dielectric BCB (FD2) / via fill (FV2)
Power/trace1 Cu (FC2)
1st dielectric BCB (FD1) / via fill (FV1)
Shield layer Cu ( FC1)
BCB
Si base

27. Reduction in area

28. 450 etch angle via to ensure good side wall
35um
How small?
450 etch angle via to ensure good side wall
No via land so diameter is line width
15um dielectric will give 55 um (from 25 um) wide line
so should only be used on shield separation layers
5um
25um

29. MFI
MicroFlex Interconnection Technology

30. Key Characteristics bond capillary of a standard wire-bonder
© IBMT
bond capillary of a standard wire-bonder
micropatterned polyimide-foil with integrated tracks and pads
pads with integrated via-holes

31. Advantages
integration of naked chips and other microelectronic components
high-density interconnects (pitch > 70µm)
3-dimensional packages
biocompatible materials
simple and reliable technology
no short circuits
no mechanical stress

32. Reliability Tests
biocompatible polyimide foil cytotoxicity tested according to ISO 10993
reliable interconnection technology electrical and mechanical tests of the interconnects according to MIL standard 883
test procedure resistance [m] before and after
temperature cycling -40°C to 150°C in air, 110h
thermal shock -180°C to 100°C in liquids, 100 cycles
humidity 95% relative 70°C, 110h
high temperature 300°C for 240h
vibration ,000Hz, gpeak = 20m/s2, 48h

33. Applications ultrasound array sensor stack with heat sinks
©IBMT
©IBMT
ultrasound array sensor
stack with heat sinks
© IBMT
retina stimulator
multiplexer module

34. References
Patents: WO ‘Contact and method for producing a contact.’ WO ‘Method for producing an electrical and/or mechanical connection between flexible thin-film substrates.’
Papers: Stieglitz, T., Beutel, H., Meyer, J.-U.: ‘Microflex - A New Assembling Technique for Interconnects’. Journal of Intelligent Material Systems and Structures, 11 (6), pp (2000). Meyer, J.-U., Stieglitz, T., Scholz, O., Haberer, W., Beutel, H.: ‘High Density Interconnects and Flexible Hybrid Assemblies for Active Biomedical Implants’. IEEE Trans. on Components, Packaging and Manufacturing Technology-Part B: Advanced Packaging (IEEE Trans. on Advanced Packaging), vol. 24 , no. 3, pp (2001).

35. Post-processing of the Micron wafers
Features of the masks
Test structures
Measurements & simulations

36. Back-plane HV bias contact
Overview of the sensor
26 identical silicon micro-strip sensors
128 1 cm long parallel strips
80 μm pitch
Each strip is a AC coupled p-n diode
300 μm
n-implant
SiO
Al-strip
80 μm
p-bulk Si
Back-plane HV bias contact
passivation

37. Top view of the micro-strip sensor
Guard rings (zero field at edge)
Serial bias resistors
Strip bond pads
HV GND pad
Guard ring
pads

38. A closer look…
Strip pad:
40x600μm2
HV pad:
40x250μm2

39. The other corner
HV and guard pads

40. Post processing fabrication
BCB layer
Open 128 holes for the strip pads (40x600μm2) and ~8 HV pads (40x250μm2).
Metal layer
Etch metal to include:
Contacts to silicon strips
Fanin?
Ground plane variants (mesh, solid, …)
Other test structures
Differential/single ended transmission lines (vary track width and separation).
Pads for passive components (solder or glue)
Pads for wire bond tests?
openings
sensor
ground plane

41. Sensor - measurements Before post-processing After post-processing IV
Connectivity from strips to 2nd metal layer
Inter-strip capacitance to 2,4,8,16 neighbours
Capacitance from a strip to metal structure above
After post-processing IV
Connectivity from strips to 2nd metal layer
Inter-strip capacitance to 2,4,8,16 neighbours
Capacitance from a strip to metal structure above
For the metal structure above the strips, we should look at a solid plane, mesh planes with different fill factors, and maybe some strip patterns with varying pitches to understand capacitance

42. Sensor – 2nd Metal layer variants
 Above the strips:
Solid plane
Meshes with 2 different fill factors
Parallel & Orthogonal 80mm pitch strip patterns
  Above the bond pads:
Ganged – for connectivity
1 strip to neighbours for capacitance
2 neighbours
4 neighbours
8 neighbours …

43. Lithography – no experience with < 50mm strips
Open issues
Cu to Al connection
Lithography – no experience with < 50mm strips
Mechanical stresses & deformation
Detector bias
Routing and decoupling
Non active part of sensor wafer

44. Commercial
A are very interested and have supplied a quote; plans have changed a bit so a revision will be required; A have previous experience with thin-film RF designs; they look like a good option.
I will require a 2nd visit with Jeff, I are interested and have previous experience, their post-processed pixel module had very fine feature sizes and was electrically flawless. Yield was low.
S (UK) is an unknown at this stage but has very good relations with CMF. We will visit them later
Will select the best company or follow a “light” tender exercise to get value for money if more than one option

45. Schedule.1

46. Schedule.2

47. Schedule (mpp file)