1. Operation of the Full Format DSSC Pixel Readout ASIC for the European XFEL
Jan Soldat, Heidelberg University
for the DSSC ASIC design groups
D. Comotti4, F. Erdinger1, C. Fiorini3, P. Fischer1, K. Hansen2, P. Kalavakuru2,
M. Kirchgessner1, M. Manghisoni4, B. Nasri3, M. Porro5, C. Reckleben2, J. Szymanski2
(Heidelberg Univ.1, DESY2, Politecnico di Milano3, Univ. de Bergamo4, MPE Munich5)

2. Novel Detectors for the European XFEL
European DESY will provide X-ray bursts
Photon Energy: 0.25 … 15 keV
→ XFEL has initiated 3 development projects: LPD, AGIPD, DSSC
Key Requirements for DSSC:
Detect single low energy X-rays ( 0.25 keV → 70 e-h+ pairs in Si)
Detect up to 104 X-rays with resolution better than Poisson limit
4.5 MHz … 1 MHz bunch rate
Possibility to process  500 pulses in each burst
 Novel 2D detectors required!

3. The DSSC Pixel Processing Chain
Sensor Pixel
Two sensor variants:
DEPFET achieves lower noise and comprises signal compression but available later
Mini-SDD type sensor for Day 0 operation
ASIC
Pixel
Front End
Mini-SDD sensor requires on-chip amplification & compression
Filter
Flip Capacitor Filter for low noise, trapezoidal weighting function, gain setting
ADC
4.5MHz frame rate  in-pixel single slope ADC (8-9bit depending on frame rate)
Digital Memory
Digital storage (800 words), readout in ~99ms XFEL gaps
XFEL Clock & Control sends VETO signals, on-chip implementation of fixed latency VETO mechanism

4. Full Size 4k Pixel ASIC Overview
First full format chip back from fabrication late September 2014
IBM 130nm, C4
4096 readout channels of
204 x 229 µm
Peripheral, IO Blocks
Pixel-row wise reference circuits
14bit DAC for ADC calibration
Temperature measurement circuit
Monitor Bus connected to all pixels
On-chip digital control
15mm
4096 Pixels
IO and Control
First samples flipped to wirebond adapters and bonded on carrier PCB

5. Readout Modes: DEPFET DEPFET with intrinsic signal compression
Filter
ADC
RAM
DEPFET with intrinsic
signal compression
Gain setting:
4 different
capacitors
4 bit
programmable
current source
with analog
fine tune

6. Readout Modes: Mini SDDFE
Filter
ADC
RAM
Passive Sensor
On chip amplification
and “Triode Compression”

7. Pixel Circuits: Single Slope ADCFE
Filter
ADC
RAM
13mm Coplanar
Waveguide
Vref of Comp = Vref of Filter!
Local ramp  allows pixel wise gain setting via I-Source (6bits)
 allows local offset through pixel delay of ramp (5bits)
 allows comparator to same voltage and slope
 is voltage drop insensitive

8. Power Supply & Decoupling
3 supply voltages
analog supply (VDDA)
digital ADC supply (VDDD_ADC)
global digital supply (VDDD_GL)
Supply currents of:
VDDA : 2.7A
VDDD_ADC: 1A
64x64 pixels
58 Power Bumps
13mm long pixel columns
Voltage drop
Row wise reference
track column
voltage drop
low duty cycle (~1/100ms)
power cycling
Only VDDD_GL stays on permanently (needed for readout during
XFEL gaps)

9. Chip operation results

10. Full Chip Operation Current injection In the input branch No injection
Data was taken in nominal XFEL operation mode (but test signal injection):
4.5MHz speed, 800 frames (mean is plotted), power cycling
 the chip is completely functional

11. Power voltage drop - column
Supply voltage is expected to drop more quickly in the lower chip rows
Local vdds / gnds can be measured via monitoring bus
Maximal drop (VDDA-GNDA) ~ 60 mV as expected.

12. Dark frame: Offset for no signal
64 x 64 Dark Frame
Internal reference buffered
by amplifier
Systematic Left/Right Difference
observed (  4.5 LSB)
Gain/Offset differences probably
introduced by hor. voltage
differences
Sufficient trimming range
(of 60%)

13. ADC performance Internal DAC High range (from 3000-600)
FE-Amplifier in Buffer mode
INL within  0.5 LSB (still affected by DAC INL of ± 0.3 LSB)
INL
DAC Noise
+ FE-Amplifier (Buffer) Noise
+ ADC Noise
Noise
DNL increases along column up to 70% of LSB
DNL

14. Full Chain Measurement with DEPFET Sensor
Measurement was taken with a mini matrix ASIC (same pixel as full format ASIC) bump bonded to an 8x8 DEPFET sensor
Noise peak
5.9 keV
6.2 keV
Very high gain setting
370 ns integration time
(1 MHz operation)
1pF integrator capacitance
Noise: 20e- rms

15. Full Chain Measurement with DEPFET Sensor
Measurement was taken with a mini matrix ASIC (same pixel as full format ASIC) bump bonded to an 8x8 DEPFET sensor
Spectra acquired simultaneously in all 64 pixels
Noise values quite similar around enc = 18 e-
Good ADC columns

16. Summary The DSSC ASIC pixel contains:
an analog filter
an ADC
a large digital memory
The ASIC runs with power cycling to cope with the load current
The first full format 14x15mm² 4k pixel prototype ASIC has been fabricated  the chip is completely functional  power connections need to be optimized to improve performance along the column
A mini matrix ASIC shows good noise performance flipped on a 8x8 DEPFET sensor