1. Register Transfer Specification And Design
Chapter 8
Register Transfer
Specification And Design
Chapter 4
Karnaugh Maps
Don’t Care Conditions
Technology Mapping
Optimization, Conversions, Decomposing, Retiming

2. Chapter preview Boolean algebra Logic gates and flip-flops3 3
Boolean algebra
Logic gates and flip-flops 6
Finite-state machine 4 6
Logic design techniques
Sequential design techniques
Binary system and data representation 2 7 5
Storage components
Combinational components
Generalized finite-state machines 8 8
Boolean Cubes for n = 1, 2, 3, and 4
Register-transfer design 9
Processor components

3. Register-transfer design
Each standard or custom IP components consists of one or more datapaths and control units.
To synthesize such IP we introduce the model of a FSM with a data (FSMD).
We demonstrate synthesis algorithms for FSMD model, including component selection, resource sharing, pipelining and scheduling.
Chapter Summary

4. High-level block diagram Register-transfer-level block diagram
Design Model
High-level block diagram
Register-transfer-level block diagram

5. Ones-counter specification
Start = 0
Start = 1
Done=0; Data = Input
Done=0; Ocount = 0
Done=0; Mask = 1
Done=0; Temp = Data AND Mask
Data = 0
Done=0; Ocount = Ocount + Temp
Done=1; Data = Data >> 1
Data = 0
Done=1; Output =Ocount

6. FSDM Definition
In Chapter 6 we defined an FSM as a quintuple < S, I, O, f, h >
where S is a set of states, I and O are the sets of input and output symbols: f : S × I S , and h : S × I O
More precisely, I = A1 × A2 ×… Ak
S = Q1 × Q2 ×… Qm
O = Y1 × Y2 ×… Yn
Where Ai, , is an input signal, Qi, is the flip-flop output and Yi, is an output signal.
To define a FSMD, we define a set of variables V = V1 × V2 ×…Vq
which defines the state of the datapath by defining the values of all variables in each state.
where IC = A1 × A2 ×… Ak as before and ID = B1 × B2 ×… Bp,
Where OC = Y1 × Y2 ×… Yn as before and OD = Z1 × Z2 ×… Zr.

7. FSDM Definition
With formal definition of expressions and relations over a set of variables we can simplify function f : ( S ×V ) × I => S ×V by separating it into two parts: fC and fD. The function fC defines the next state of the control unit
fC : S × IC × STAT => S
while the function fD defines the values of datapath variables in the next state
fD : S × V × ID => V
fD : {fDi : V × ID => V : { Vj = ej | Vj elof V, ej elof Expr ( V × ID )}}
Also,
hC : S × IC × STAT => OC
and
hD : S × V × ID => OD

8. FSMD specification of Ones-counter
State and output table
State and output table with variable assignments State-action table

9. Algorithmic-State-Machine
Graphic representation of FSMD model
Equivalent to state-action table
Similar to a flowchart used for program description

10. ASM Symbols

11. ASM rules
Rule 1: The chart must define a unique next state for each state and set of conditions.
Rule 2: Every path defined by the network of condition boxes must lead to another state.
Undefined next state Undefined exit path

12. ASM chart for Ones-counter
(a) State-based (Moore) chart (b) Input-based (Mealy) chart

13. State-action tables for Ones-counter
State-based table

14. State-action tables for Ones-counter
Input-based table

15. Logic schematics for Ones-counter
D2 = Q2(next) = s2DataLSB + S3 + S4(Data 0)’
= Q1Q’0Data’LSB + Q1Q0 + Q2Q’0(Data 0)’
D1 = Q1(next) = s1 + s2DataLSB + s4(Data 0)
= Q’2Q’1Q’0 + Q1Q’0DataLSB + Q2Q’0(Data 0)
D0 = Q0(next) = s0Start + s2DataLSB + s4(Data 0)’
= Q’2Q’1Q’0Start+Q1Q’0DataLSB+Q2Q’0(Dara 0)’
S1= s4 =Q2Q’0
S0 = s2 + s4 = Q1Q’0 + Q2Q’0
E = s3 = Q1Q0
Load =s1 = Q’2Q’1Q0
Done = Output enable = s5 = Q2Q0
State-based version

16. Logic schematics for Ones-counter
D1 = Q1 ( next ) = s1+s2 = Q’1Q0 + Q1Q’0
D0 = Q0 ( next ) = s0Start + s2( Data 0 )’
= Q’1Q’0Start + Q1Q’0 ( Data 0 )
S1 =s2( Data 0 ) = Q1Q’0( Data 0 )
S0 = s1 + s2( Data 0 ) = Q’1Q0 + Q1Q’0( Data 0 )
E = s2DataLSB = Q1Q’0DataLSB
Load = s1 = Q’1Q0
Done = Output enable = s3= Q1Q0
Input-based version

17. Register-transfer synthesis
Block diagram
Register sharing
Functional unit sharing
Bus sharing
FlowChart of Square-root approximation

18. Resource usage in square-root approximation
Variable usage
Operation usage
Flowchart of
Square-root approximation

19. Simple library components
Absolute value unit
(version 1)
(b) Absolute value unit
(version 2)
(c) Min unit
(d) Max unit
(e) Min/Max unit
(f) 1-bit right shifter
(g) 3-bit right shifter
(h) 1-bit/3-bit right shifter
(i) Adder
(j) Subtractor
(k) Adder/Subtractor

20. Connectivity requirementsa b t1 t2 x y t3 t4 t5 t6 t7
abs1 1
abs2
min
max
>>3
>>1 - +
Flowchart of Square-root approximation
Connectivity table

21. Register sharing (Variable merging)
Grouping of variables with non-overlaping lifetimes
Each group shares one register
Grouping reduces number of registers needed in the design
Two algorithms: left-edge and graph-partitioning

22. Left-edge algorithm

23. Register sharing by left-edge algorithmX b t1 t2 x y t3 t4 t5 t6 t7
R1 = {a, t1, x, t7}
R2 = {b, t2, y, t4, t6}
R3 = {t2, t5 }
Sorted list of variables
Register assignments
Datapath schematic
Flowchart

24. Merging variables with common sources and destination
Partial Flowchart
Datapath without register sharing
Datapath with register sharing

25. Graph partitioning algorithm
(a) Initial compatibility graph
General partitioning algorithm

26. Graph partitioning algorithm for SRA
(a) Initial compatibility graph
(b) Compatibility graph after merging t3, t5 and t6
(c) Compatibility graph after merging t1, x and t7
(d) Compatibility graph after merging t2 and y
(e) Final compatibility graph
Flowchart

27. Register assignment generated by the graph-partitioning algorithm
R1 = [ a , t1 , x , t7 ]
R2 =[b , t2 , y , t3 , t5 , t6 ]
R3= [ t4 ]
Register assignments
Datapath

28. Functional unit sharing (operator merging)
Group non-concurrent operations
Each group shares one functional unit
Sharing reduces number of functional units
Prioritized grouping by reducing connectivity
Clustering algorithm used for grouping

29. Functional unit sharing
Partial Flowchart
Non-shared design
Shared design

30. Complex library components
Unit for computing minimum, maximum and absolute value
Unit for computing addition, subtraction, minimum and maximum
Unit for computing addition, subtraction, and absolute value
Unit for computing addition, subtraction, minimum, maximum and absolute value

31. Operator merging for SRA implementation
(a) Compatibility graph
(b) Cost table
(c) Merging alternative
(d) Cost table
Flowchart
(e) Merging alternative
(f) Cost table

32. Datapath connectivity
(a) Datapath schematic for unit allocation from figure 8.22 (c)
FlowChart
(b) Datapath schematic for unit allocation from figure 8.22 (e)

33. Priorities in unit merging
(a) Partial Flowchart
(b) Design without merged units
(c) Design with merged units

34. Unit merging for SRA datapath
(b) Compatibility graph after merging of + and _
(a) Compatibility graph
(c) Compatibility graph after merging of min, + and _
(d) Final graph partitions
Flowchart

35. SRA datapath generated by prioritized partitioning
R1 = [ a, t1, x, t7 ]
R2 = [ b, t2, y, t3, t5, t6 ]
R3 = [ t4 ]
AU1 = [ |b| / min / + / - ]
AU2 = [ |a| / max /]
SH1 = [ >>1 ]
SH2 = [ >>3 ]
(a) Register and functional unit allocation
(b) Datapath schematic

36. Bus sharing ( connection merging )
Group connections that are not used concurrently
Each group forms a bus
Connection merging reduces number of wires
Clustering algorithm is demonstrated

37. Connection merging in SRA datapath
Bus1 = [ A, C, D, E, H ]
Bus2 = [ B, F, G ]
Bus3 = [ I, K, M ]
Bus4 = [ J, L, N ]
(a) Datapath for SRA
(e) Bus assignment
(c) Compatibility graph for input buses
(d) Compatibility graph for output buses
(b) Connectivity usage table

38. Connection merging in SRA datapath
Bus1 = [ A, C, D, E, H ]
Bus2 = [ B, F, G ]
Bus3= [ I, K, M ]
Bus4 = [ J, L, N ]
Datapath for SRA
Bus assignment
(f) Bus oriented datapath

39. Register merging Group register with non-overlapping accesses
Each group assigned to one register file
Register grouping reduces number of ports, and therefore number of buses
Demonstration with clustering algorithm

40. Register merging R1 = [ a, t1, x, t7 ] R2 = [ b, t2, y, t3, t5, t6 ]
R3 = [ t4 ]
(a) Register assignment
(b) Register access table
(c) Compatibility graph
ASM Chart
(d) Datapath schematic

41. Chaining and multi-cycling
Chaining allows serial execution of two or more operations in each state
Chaining reduces number of states and increases performance
Multi-cycling allows one operation to be executed over two or more clock cycles
Multi-cycling reduces size of functional units
Chaining and multi-cycling are used on noncritical paths to improve resource utilization and performance

42. SRA datapath with chained units
(b) Datapath schematic
(a) Flowchart

43. SRA datapath with multi-cycle units
(b) Datapath schematic
(a) Flowchart

44. Pipelining
Pipelining improves performance at a very small additional cost
Pipelining divides resources into stages and uses all stage concurrently for different data ( assembly line principle)
Pipelining principles works on several levels:
Unit pipelining
Control pipelining
Datapath pipelining

45. Pipelined arithmetic unit

46. SRA datapath with single AU
(b) Datapath schematic
(a) Flowchart

47. Datapath with pipelined functional unit
(a) Datapath with
pipelined AU
(b) Timing diagram

48. (b) Pipelined datapath (c) Register and functional unit assignment
Datapath pipelining
(b) Pipelined datapath
R1 = [ a, t1 ] R3 = [ t3, t5, t6, t7 ]
R2 = [ b, t2 ] R4 = [ x ]
AU1 = [ abs/min/max ] R5 = [ t4 ]
AU2 = [ +/-/max ]
(a) Flowchart
(c) Register and functional unit assignment

49. (b) Pipelined datapath
Datapath pipelining
(b) Pipelined datapath
(d) Timing diagram

50. Timing diagram for datapath pipeline with pipelined units

51. Pipelined FSMD implementation
(a) Standard FSMD implementation
(b) FSMD implementation with control and datapath pipelining

52. Flowcharts for pipelined FSMDs
(b) FSMD implementation with control and datapath pipelining
(b) Flowchart for control pipeline with status register
(c) Flowchart for control pipeline with status register and control registers
(a) Flowchart
(d) Flowchart for control and datapath pipeline

53. Scheduling
RT description such as ASM chart specifies data operations in each state
Flowcharts or programming languages do not have states, but only specify order in which operations are executed.
Scheduling transforms flowcharts or programs with RT descriptions
Two types of scheduling
(a) resource constrained (resource given, minimize time)
(b) time constrained (time given, minimize resources)

54. Control/dataflow graph for SRA
(a) Flowchart
(b) Control/Data flow graph

55. Basic schedules
(a) ASAP schedule
(a) ALAP schedule

56. List scheduling algorithm

57. Resource-constrained scheduling
(a) ASAP
(b) ALAP
(c) Ready list with nobilities
(d) RC schedule

58. Time-constrained scheduling

59. TC schedule for SRA algorithm
(a) ASAP
(b) ALAP
(c) TC schedule

60. Probability distribution graph before, during and after TC scheduling
(a) Initial probability distribution graph
(b) Distribution graph after max, + and – were scheduled
(c) Distribution graph after max, + and –,>>3 and >>1 were scheduled
(c) Distribution graph for final scheduled

61. Chapter summary FSMD model RT specification with
We introduced RT design:
FSMD model
RT specification with
Procedure for synthesis from RT specification
Design Optimization through
Design Pipelining
Scheduling of flowcharts
Static-action tables
ASM charts
Register sharing
Unit chaining
Functional unit sharing
Multi-clocking
Bus sharing
Unit pipelining
Control pipelining
Datapath pipelining

62. Example 7.1
Map Representation