1. The UniBoard A RadioNet FP7 Joint Research Activity, 9 partners
Multi-purpose, scalable, high performance, generic interfaces (10GE, DDR3)
Per board: 8 Altera Stratix IV FPGAs (40 nm), 2  16  10 Gbps, each front node to all back node mesh (more info: see poster)
JIVE: project lead, ASTRON: hardware development
KASI, INAF, ShAO, Universities of Bordeaux, Orléans, Manchester, Oxford: various applications
Prototype undergoing tests now
Currently under development: VLBI correlator (JIVE), digital receiver (INAF, BORD), pulsar binning machine + RFI mitigation (UMAN, UORL)
Coming soon: APERTIF correlator + beam former (ASTRON), all-station LOFAR correlator (ASTRON + University of Amsterdam, Oxford), more applications on the way
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2. SKA-like configurations
Corner turning done in network
256 telescope correlator, 1GHz, 2 pol, 8 bits
Could be built now using existing hardware (infiniband switches)
320 UniBoards, 16 switches
Future scalability depends on capacity of future switches
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3. SKA-like configurations (2)
Combination of UniBoards into larger systems via backplane
Will be developed through NWO-funded ExBox project (JIVE-ASTRON collaboration)
Application in APERTIF (ASTRON)
Correlator for 12 dual pol dishes, 300 MHz bandwidth, 37 beams
32 UniBoards
Application in AARTFAAC (University of Amsterdam-ASTRON collaboration)
Correlator for 576 signal paths, ~ 17.5 MHz bandwidth
12 UniBoards
APERTIF correlator
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4. Next: UniBoard2
Possible Joint Research Activity in RadioNet3, follow-up of current project, start date 2012 (if approved by EC...)
Received strong support from RadioNet community
Same basic idea, development of generic hardware complemented by a number of applications
Consolidate and build on expertise obtained through UniBoard project
Strong emphasis on power efficiency (green computing)
Production-ready in 2015/2016
Complete re-design, using the next generation 28 nm FPGAs, possibly one generation beyond that (some slack in start date of project)
Non-leaded components
Possible use of 40GE, 100GE
Investigation into effects of hard-copy and partial hard-copy
Tuning of algorithms and firmware design to minimize power consumption
Balancing of system parameters and performance to minimize power consumption
Standardized interfaces and coding conventions to facilitate sharing and re-use of firmware blocks among developers of different applications
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5. Useful milestones
End of 2010, a well-documented power-consumption budget for the UniBoard
Mid-2011 (after implementation of correlation and digital receiver design) , a report on the suitability of the specific FPGAs we have chosen (size, number of DSPs, amount of logic) and implications for a SKA implementation
Report on the computing demands posed by different configurations and implications for hardware platform (length of baseline, frequency, number of bits, field of view vs. frequency smearing, bandwidth smearing)
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