1. Overview and System Design for ESS LLRF Systems
Anders J Johansson, Lund University, sweden

2. European Spallation Source
5 MW Neutron source
2 GeV proton linac
Pulsed at 14 Hz, 2.86 ms long pulses.
Rotating tungsten target

3. ESS Accelerator 1 RFQ 3 Pillbox buncher cavities in MEBT.
Source
LEBT
RFQ
MEBT
DTL
Spokes
Medium b
High b
HEBT
Target
MHz
704.42MHz
Pulsed
14 Hz
3.6 MeV
90 MeV
216 MeV
561 MeV
2000 MeV
62.5 mA
1 RFQ
3 Pillbox buncher cavities in MEBT.
5 Drift Tube Linac sections.
26 Superconducting spoke cavities.
36 Superconducting medium-b cavities.
84 Superconducting high-b cavities.

4. ESS RF power amplifiers
One power amplifier per accelerating cavity
2.8 MW Klystron for RFQ
30 kW Solid State for Buncher
2.8 MW Klystron for DTL
2x200kW Tetrode combined for Spoke
1.5 MW Klystron for Medium- Beta Elliptical
1.2 MW IOT for High Beta Elliptical

5. Field Stability
Current requirements for regulation accuracy of the cavity field.
RFQ
+/- 0.2 % RMS amplitude
+/- 0.2 o RMS*
Normal Conducting
+/- 0.2 o RMS
Super Conducting
+/- 0.1 % RMS amplitude
+/- 0.1 o RMS
Relaxed requirements
for initial 10 us.
Time
Cavity
Field
Beam
2.86 ms
*Relative the phase reference line. All other phase requirements relative the beam.

6. Timing and Phase Reference
MRF timing system in gallery distributes triggers.
Phase reference line in tunnel.

7. RF Cell LLRF: PI-control Adaptive feedforward Inner klystron loop
Beam current variation compensation

8. High level LLRF architecture
Procedures
Schemes that involve longer times and multiple pulses.
Algorithms
Updates that take place between pulses (68 ms).
Functions
Real-time control within a pulse (3.5 ms).
Procedures
Scripts
CPU
EPICS
Algorithms
Software
CPU
PCIe
LLRF
Functions
Firmware
FPGA

9. Platform: MTCA.4 Modular design Adaptable to different cavities.
Facilitates incremental upgrades
Simplifies end of life management
Temperature controlled rack

10. MTCA cards in crate for RFQ
RFQ has 22 sensors, uses multiple acquisition cards.
MCH
FPGA+ADC/DAC+RTM
CPU
FPGA+ADC/DAC+RTM
Timing
FPGA+ADC/DAC+RTM
FPGA+ADC/DAC+RTM
PSU
PSU

11. 704.42 MHz Medium-b MTCA.4 LLRF CPU Timing Timing FPGA/ADC RF/VM
CB control on backplane
Timing triggers
MCH supervision
External I/O
Ethernet on backplane
CPU
LO-generation
Phase reference
Cavity Pickup
VM out
PreAmp Out
PowerAmp out
PowerAmp Refl
Cavity In
Cavity Refl
Clk
Timing
LO/REF
Timing
FPGA/ADC
RF/VM
Interlock
Modulator Voltage
Beam current
Vectormodulator out
FPGA PZ
Piezo 1
Piezo 2
MCH
Fan Tray x 2
EPICS, Supervision
PSU x 2
230 V AC

12. Tuning
Slow tuners
The cavities are mechanically tuned to the right frequency.
Temperature for RFQ
Slug tuners for DTL and buncher cavities.
Cavity deformation for spoke and elliptical cavities.
The stepper motors for the cold cavities are within the cryomodule.
The motor controllers will be controlled from the LLRF system over EPICS.

13. Tuning
Fast tuners
The superconducting cavities have additional piezo actuators.
There are two piezo actuators per cavity for redundancy.
Will be used to reduce Lorenz force detuning.
Triggered by timing system
Control electronics integrated into LLRF crate.

14. Status Two test benches up and running at Lund University 352.21 MHz
Test benches controlled from a central ”control room” computer and screens.
One prototype running at Freia test hall at Uppsala University.

15. ESS LLRF Collaboration
The LLRF system is designed by Lund University, Sweden.
The LLRF hardware for MHz part is planned to be delivered from ESS Bilbao, Spain.
The LLRF hardware for MHz is planned to be delivered from Polish Electronics Group, Poland.
One RTM card designed by SLAC under contract.
In addition, all collaborators are doing additional design work on separate components of the complete system.

16. ESS RF and LLRF presentations at LLRF 2015
Olof Troeng ”Cavity field control for ESS” (Tuesday)
Fredrik Kristensson ”ESS digital LLRF prototype and testbenches” (Wednesday)
Anders Sunesson ”RF system development at ESS”, (Thursday)
Anders J Johansson ”Overview and system design for ESS LLRF systems (Thursday)
Rihua Zeng ”Investigation of energy efficiency improvements in LLRF control at ESS” (Thursday 13:55)
Anders Svensson ”ESS phase reference signal distribution” (Friday 9:55)
Bo Bernhardsson