1. 3D IC Reliability
Xinxin Yu, Hao Wu

2. Packaging Technology Evolution

3. 3D IC

4. Requirements for 3D (TSV) IC Success

5. 3D (TSV) IC Design Flow Vision

8. Reliability Issues Common Design Electromigration Self-heating
Hot carriers
Latchup
Overvoltage failure
3D IC
Stress

10. 3D Model Construction for Thermal and stress
ANSYS

11. Thermal Equation

12. Parameters

13. Boundary Condition

14. Simulation results from Cadence

15. Current and voltage inputs

16. Application of Submodeling

17. Temperature Distribution

18. CTM-based thermal analyzer
Chip Thermal Mode
CTMs are first generated for all the chips in 3D IC or SiP.
The thermal analyzer then simulates and updates temperature on each of the chips
Continue looking up in CTMs for updated power maps and recalculate temperatures, until the total power on each chip converged
Detailed full chip sub-models are then constructed from the metal layer distributions in CTM and physical chip geometry

19. Power density map

21. TSV Induced Stress and Reliability

22. 3D IC Stress Reliability

23. Single TSV with various structural configurations
Due to the thermal expansion mismatch between constituent materials, the fabrication of TSVs can induce thermal stresses to degrade the performance of stress sensitive devices.
Thermo-Mechanical Reliability of 3-D ICs containing Through Silicon Vias
Kuan H. Lu, Xuefeng Zhang, Suk-Kyu Ryu*, Jay Im, Rui Huang*, and Paul S. Ho, 2009 Electronic Components and Technology Conference

24. Two-by-two copper TSV array
the methodology will be extended to analyze the stress interaction in TSV arrays

25. Analytical Plane Strain Approximation
When two TSVs are aligned along the y- direction, the normal stress is intensified and the shear stress is suppressed in the space
In contrast, the normal stress is suppressed and the shear stress is intensified while two TSVs are aligned in the diagonal direction.
It suggests that the stress interaction between TSVs is directional dependent, and the TSV arrays can be arranged accordingly to minimize the thermal stresses.

26. Thermal Stress Induced Crack Driving Force
stress intensity factor
The result suggests the zigzag structure effectively suppresses the crack driving force and improve the thermo-mechanical reliability

27. Electromigration traditional mass balance equations parameters
EM refers to the mass transport in metal structures. It is affected by geometrical shapes, temperature distribution, mechanical stress, current density, and material properties
q is the total atomic flux, c is the atomic concentration
with initial value c0, j is the current density, Q is the heat of
transport, σ is the hydrostatic stress, and D is the diffusivity.
Modeling of Electromigration in Through-Silicon-Via Based 3D IC
Jiwoo Pak, Mohit Pathak, Sung Kyu Lim and David Z. Pan
2011 Electronic Components and Technology Conference

28. Modeling and Results

29. atomic concentration variation to reach a certain threshold (TΔC)
point ‘C’ tends to fail first, and points ‘D’,‘H’, ‘I’ fail relatively early. These four points tend to have the maximum stress gradients around them. Due to difference in the thickness of the top landing pad and the bottom landing pad and also, due to the difference in the properties of the materials surrounding them.
By increasing the TSV radius, the amount of stress gradient around stress-hot region gets larger, therefore ‘B’, ‘C’, ‘D’, ‘I’, ‘H’, ‘G’ fail earlier than the smaller radius of TSV.
‘C’, ‘D’, ‘H’, ‘I’ tend to fail earlier with pad size increases due to greater mismatch in the landing pad size and the TSV radius causes larger stress gradients.
Wire Connection

30. EM modeling of wires in a 3D IC

31. Design Guide
TSVs with smaller size lead to smaller stress gradients and are thus less likely to fail due to TSV-induced stress.
Larger variation in the dimensions of the TSV structure may cause greater stress gradients thus making it more likely to fail.
The wire and landing pad interface should be as far as possible from the TSV structure to reduce the impact of stress induced failure.
Via-last structure tends to have greater stress gradient but lower current density. Thus Via-last structure may cause more failures due to TSV-induced stress.

32. In summary 3D IC Yield 3D IC reliability (self-heating)
TSV fabrication causes thermal stress
Specified keep-away-zone needed for stress sensitive devices
Crack driving force induced (serious problem)
3D IC reliability (self-heating)
Thermomigration
Electromigration
TSV chips warpage
Self-heating simulations developed
Heat dissipation discussed