1. DuraCache: A Durable SSD cache Using MLC NAND Flash Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen IEEE Design Automation Conference (DAC)
Heo, Sang-Bok

2. Introduction NAND flash-based solid-state drives(SSD)
SSD have gained popularity in datacenter storage
Whether SSD could replace HDD is controversial
SSD as cache is a cost-effective solution
Major storage vendors gave announced their SSD cache solutions[2][3][4]

3. Introduction SSD cache’s advantage
Can be deployed in both host servers and storage servers
One benefit is acceleration applications that demand high storage performance
online transaction processing
Reads that hit the SSD caches can be directly served by the SSD caches

4. Introduction Two types of flash memory Single-level cells(SLC)
stores one bit of information per cell
Multi-level cells(MLC)
Stores multiple bits by dividing the threshold voltage of a cell into multiple levels
MLC-based SSD caches can have up to ten times more capacity than SLC ones at the same cost
MLC have low-endurance issue
SSD cache solutions have to adopt SLC flash

5. Introduction DuraCache It is critical to resolve the endurance issue
Based on the design principles of fault tolerance and graceful degradation
Features two mechanisms, its Error Transformation and Dynamic-Rate SSD(DR-SSD)

6. Design of DuraCache Error Transformation
The first technique of DuraCache is fault tolerance through Error Transformation
Error Transformation handles uncorrectable errors by converting them into cache misses that bring in valid data from HDD arrays

7. Design of DuraCache
In industrial standards, data read need to guarantee ≤ 10 −16 bit error rate(BER) Flash reaches its end of lifetime once its error rate exceeds 10 −16 after error correction

8. Design of DuraCache
The key idea behind Error Transformation is to detect errors that cannot be corrected by ECC and bring in valid data from HDD arrays accordingly Checksums are added to data when flash is written Checksums are validated when the data are read out of the flash

9. Design of DuraCache
Checksum Selection Hit Count Impact

10. Evaluation
We target at a modern 25-nm two-bit MLC NAND flash memory Lists the six scenarios we evaluate

11. Evaluation Lifetime Improvement
B1 and B2 both can handle a BER of 4.5 ×10 −4
B3 adopts DCT, BER of 1 ×10 −3
D1, ET scheme, can handle a BER of 1.2 ×10 −3
D2 can handle a BER of 4.5 ×10 −3
D3 can handle a BER up to 6.7 ×10 −3
D3 can deal with a 6.7 time higher BER than B3 with similar ECC complexity

12. Evaluation
D3 can sustain 59k P/E cycles datacenter workload such as TPC-C can cause SSD caches to be program and erased 39 cycles per day Sustain 4.1 years of service life assuming a write-intensive workload like TPC-C
59 × ×365 =4.1

13. Conclusions
We present DuraCache that features the prosed Error Transformation and Dynamic-Rate SSD schemes SSD caches can have 4.1-year service life assuming a write- intensive datacenter workload like TPC-C