1. STICK Diagrams UNIT III : VLSI CIRCUIT DESIGN PROCESSES VLSI DESIGN
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STICK Diagrams
UNIT III : VLSI CIRCUIT DESIGN PROCESSES
VLSI DESIGN
31/01/2009
VLSI Design

2. The MOS (Metal-Oxide-Semiconductor) Transistor
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The MOS (Metal-Oxide-Semiconductor) Transistor
Polysilicon
Aluminum 2

3. Review - Transistor Structure
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Review - Transistor Structure

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n-Channel MOSFET
Gate
Drain
Source L W
LEFF
Bulk

5. Static Complementary CMOS
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Static Complementary CMOS
VDD
In1
PMOS only
In2
PUN …
InN
F(In1,In2,…InN)
In1
In2
PDN …
NMOS only
InN
One and only one of the networks (PUN or PDN) is conducting in steady state
PUN and PDN are dual logic networks

6. Complementary CMOS Logic Style
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Complementary CMOS Logic Style

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VLSI Design

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VLSI Design

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VLSI Design

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VLSI Design

11. Stick diagrams (1) A stick diagram is a cartoon of a layout.
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Stick diagrams (1)
A stick diagram is a cartoon of a layout.
Does show all components/vias relative placement.
Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.
Useful for planning layout
relative placement of transistors
assignment of signals to layers
connections between cells
VLSI Design

12. We represent the different wiring layers with different colors
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We represent the different wiring layers with different colors
Diffusion - green / yellow
Poly red
Metal1 - blue
Metal2 - purple / orange
Wires on the same layer that touch ALWAYS connect. There is no way to jumper a wire without changing layers.
Wires on different layers can be cross without connections. To form connections between different layers you need to explicitly draw a contact

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Transistors
Transistors are formed when poly (red) crosses diffusion (green or yellow). .
red
green
connection
not connected
transistor

14. Stick Diagrams – Some rules
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Stick Diagrams
Stick Diagrams – Some rules
Rule A
When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.

15. Stick Diagrams – Some rules
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Stick Diagrams
Stick Diagrams – Some rules
Rule B
When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact.
--If electrical contact is needed we have to show the connection explicitly

16. Stick Diagrams – Some rules
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Stick Diagrams – Some rules
Rule C
When a poly crosses diffusion it represents a transistor. S D S D
Note: If a contact is shown then it is not a transistor.

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18. Stick Diagrams Inverter  Presents wires and transistors
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 Presents wires and transistors
Stick Diagrams
 Positioning is related.
 Gate topologies and layout strategies.
-Contains no dimensions
-Represents relative positions of transistors
VDD
VDD S S D
Inverter D
Vin
Out
Vout S D D In S
GND 18 18

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NAND Gate:

20. Stick Diagram for CMOS NOR
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Stick Diagram for CMOS NOR A B
Vdd
Gnd
out S A B
out S D D D S S D D D S S D D S S

21. Stick Diagram of NOR gate
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Stick Diagram of NOR gate S D S S

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CMOS NAND A B
Vdd
Gnd
out A B
out S S S D D S D D S D S D S D S

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VDD S D S D D S S S S D D S D

24. CMOS Gate Design: 4-input CMOS NOR gate
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CMOS Gate Design: 4-input CMOS NOR gate

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4-input NOR gate
Y=A+B+C+D

26. CMOS Gate OUT = D + A· (B+C) B A C D A D B C 26 EE141 EE141 26
Shown synthesis of pull up from pull down structure 26 26

27. CMOS Gate1
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OUT = (D +E) A+B C

28. Construction of LOGIC Graph
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Construction of LOGIC Graph
First convert CMOS circuit in to graph
Vertices in the graph are Source/Drain connections
Edges in the graphs are transistors gates that connect particular Source/Drain Vertices
Two graphs will result: one for Pull-Up Network(PUN)and one for Pull-Down Network(PDN)

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Euler Graph Technique can be used to determine if any complex CMOS gate can be physically laid out in an optimum fashion
1)Start with either NMOS or PMOS tree (NMOS for this example) and connect lines for transistor segments, labeling devices, with vertex points as circuit nodes.
2)Next place a new vertex within each confined area on the pull-down graph and connect neighboring vertices with new lines, making sure to cross each edge of the pull-down tree only once.
3)The new graph represents the pull-up tree and is the dual of the pull-down tree.

31. Minimize area-Eulers path
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Minimize area-Eulers path Z

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Euler graph APPROACH

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34. Stick Diagram using Euler Graph Method
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Stick Diagram using Euler Graph Method

35. Stick Diagram Optimum Gate Ordering
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ALL IN ONE
Stick Diagram Optimum Gate Ordering
Find a Euler path in both the pull-down tree graph and the pull-up tree graph with identical ordering of the inputs.
Euler path: traverses each branch of the graph exactly once!
By reordering the input gates as E-D-A-B-C, we can obtain an optimum layout of the given CMOS gate with single actives for both NMOS and PMOS devices (below).

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Stick diagram

37. Stick Diagram Drawing : CMOS
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Stick Diagram Drawing : CMOS
Steps
Implement the expression in CMOS Logic
Find all Euler paths that cover the graph
Find n and p Euler paths that have same labeling
Draw Stick diagram for optimization of diffusion areas

38. Stick Diagrams C • (A + B) PDN vs. PUP Series Parallel Logic Graph
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Stick Diagrams
C • (A + B)
VDD
PDN vs. PUP
Series Parallel A C
Logic Graph B
X = C • (A + B) C
Systematic approach to derive order of input signal wires so gate can be laid out to minimize area
Note PUN and PDN are duals (parallel <-> series)
Vertices are nodes (signals) of circuit, VDD, X, GND and edges are transitions A B A B C
GND 38 38

39. Two Versions of C • (A + B)
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Two Versions of C • (A + B)
Ordering the input terminals  A C B
Ordering the input terminals  A C B X C A B
VDD
GND A B C X
VDD
GND
Line of diffusion layout – abutting source-drain connections
Note crossover eliminated by A B C ordering
NMOS
PMOS
Diffusion
Poly-silicon 39 39

40. OAI Logic Graph: OR-AND-INVERT
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OAI Logic Graph: OR-AND-INVERT A C
Logic Graph B D
X = (A+B)•(C+D) C D A B C D A B 40 40

41. Example: x = AB + CD X A B C D VDD Euler paths {A B C D } D C A B
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Example: x = AB + CD
VDD
Euler paths {A B C D } D C A B
X = AB + CD C B
VDD D A X
GND
GND A B C D
Stick diagram for ordering { A B C D } 41 41

42. Dimensionless layout entities Only topology is important
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Dimensionless layout entities
Only topology is important
Final layout generated by “compaction” program

43. Stick Diagram - Example II
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Stick Diagram - Example II
Power A
Out C B
Ground

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Consistent Euler Path
An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph
Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X C i
VDD X
A path through all nodes in the graph such that each edge is visited once and only once.
The sequence of signals on the path is the signal ordering for the inputs.
PUN and PDN Euler paths are (must be) consistent (same sequence)
If you can define a Euler path then you can generate a layout with no diffusion breaks
A B C
C A B
B C A  no PDN
B A C
A C B -> no PDN
C B A B A j A B C
GND
For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)

45. Example:1. Draw Logic Graph
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Example:1. Draw Logic Graph
Identify each transistor by a unique name of its gate signal (A, B, C, D, E in the example of Figure 1).
Identify each connection to the transistor by a unique name (1,2,3,4 in the example of Figure 1).

46. Example:2. Define Euler Path
Euler paths are defined by a path the traverses each node in the path, such that each edge is visited only once.
The path is defined by the order of each transistor name. If the path traverses transistor A then B then C. Then the path name is {A, B, C}
The Euler path of the Pull up network must be the same as the path of the Pull down network.
Euler paths are not necessarily unique.
It may be necessary to redefine the function to find a Euler path. F = E + (CD) + (AB) = (AB) +E + (CD)

47. Example:3.Connection label layout
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Example:3.Connection label layout

48. Example:4.VDD, VSS and Output Labels
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Example:4.VDD, VSS and Output Labels

49. Example:5.Interconnected
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Example:5.Interconnected

50. Sticks Diagram 1 V 3 In Out GND Dimensionless layout entities
Stick diagram of inverter
Dimensionless layout entities
Only topology is important
Final layout generated by “compaction” program

51. Stick Diagram - Example II
Power A
Out C B
Ground

52. DRAW THE STICK DIAGRAMS
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Z=ABCD
Z=A+B+C+D
Z=ABC+D
Z=(AB+C) D
Z=(A+B+C)D
Z=A(B+C)+DE
DRAW THE STICK DIAGRAMS

53. References
CMOS Digital Integrated Circuits Analysis And Design, Sung-mo Kang,Yusuf Leblebici
Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003.
Digital Integrated Circuits - John M. Rabaey, PHI,

54. ---A small group of thoughtful committed citizens can change the world
---A small group of thoughtful committed citizens can change the world .Indeed it is only thing that ever has…