1. Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching
Yu Hu1, Zhe Feng1, Lei He1 and Rupak Majumdar2
1Electrical Engineering Dept., UCLA
2Computer Science Dept., UCLA
Presented by Yu Hu
Address comments to

2. Outline Background and Motivation Preliminaries
Robust Resynthesis Algorithms
Experimental Results
Conclusion and Future Work

3. Background Late CMOS scaling reduces device reliability
Single event upset (SEU) due to cosmic rays
Affects configuration SRAM cells in FPGAs
Permanent soft error rate (SER)
Need rewriting SRAM for recovery
Affects combinational circuits and FFs
Transient SER
Can be recovered in multiple clock cycles
Due to the aggressive CMOS scaling, device reliability is reduced. Particularly, single event upset due to cosmic rays can cause permanent defects which cannot be fixed until reconfiguration, and transient defects which can be recovered in a few clock cycles.
In this work, we consider both permanent and transient defects.

4. Fault Tolerance Techniques for FPGAs
The fault tolerance techniques for programmable logic devices have been studied for a long time.
For measure the quality of a particular fault tolerance technqiue, we consider defect coverage, area/delay overhead, and the design cost. Specifically, we’d like to achieve high defect coverage with negaligible cost.

5. Fault Tolerance Techniques for FPGAs
Our work
Low-cost, complementary approach to existing techniques!
Let’s first see the pros and cons of the existing fault tolerance techniques for PLDs.
One of the most popular techniques is triple modular redundancy associated with high area/delay overhead.
To cope with resource overhead by TMR, FPGA vendors proposed to use redundant columns or rows to mask faults. However it requires extra efforts in testing and synthesis while having relatively low fault coverage.
For those mission-critical applications, we can perform chip-wise testing and synthesis. However, its excessive testing and synthesis make the massive production very expensive.
As a tradeoff between fault coverage and synthesis cost, a set of precompiled multiple configurations can be applied for one application, and the one with the best fault tolerance is chosen.
In this paper, we propose stochastic synthesis, which assumes randomly distributed defects and synthesis to maximize the stochastic yield. It achieves acceptable fault coverage with the lowest overhead and cost. Note that the proposed stochastic synthesis can be used as a complementary apporach to existing technqiues to further increase the robustness with no extra cost.
[A. Djupdal and P. Haddow, Yield Enhancing Defect Tolerance Techniques for FPGAs, MAPLD 2006]

6. Stochastic Synthesis and Logic Masking
Stochastic synthesis assumes probabilistic logic values to model effect of random defects
Break the conventional Boolean view which assumes deterministic Boolean ‘0’ and ‘1’ values
Key to stochastic synthesis: Logic Masking
Masked faults
First let’s see how logic masking affect fault tolerance for single function by an example. Consider a boolean function g=!b+!a*!c, we perform different Boolean matching algorithms to map them into 2-input LUTs, and obtain the following two different mapping results, one with 3 LUTs and one with 2 LUTs.
Assuming the same defect rate of a LUT, we curve the fault rate of the two mappings. Mapping (b) is more fault-tolerable and the difference is up to 20%.
We now use the logic masking to analyze the two circuits. For circuit (b), if “b”=0, any faults up to the output of the first LUT is masked. But for circuit (a), even when “b”=0, if any of the configuration bits is defected, the output could go wrong. 1

7. Stochastic Synthesis and Logic Masking (cont.)
Stochastic Synthesis intelligently places logic masking.
Logic Masking reduces the probability of the propagation of random faults
Maximizes the stochastic yield
However, logic synthesis to maximize yield rate w/o explicit redundancy and testing has not been studied for fault tolerance!
Key questions
How much does logic masking affect robustness?
How and where to place logic masking?
Essentially, stochastic synthesis works because of the propagation of faults can be masked by logics in a circuit.
The implementation of a stochastic synthesis requires intelligently placement of the logic masking by leveraging the programmability of FPGAs
Now the two key questions that i’m going to answer are:
How much does logic masking affect fault tolerance?
Where to place logic masking?

8. How much Logic Masking Affect Robustness?
Different synthesis leads to different logic masking.
Stochastic synthesis maximizes logic masking!
18 synthesis solutions obtained by Berkeley ABC
(for MCNC i10, LUT bit fault rate = 0.1%)
Next we show that different synthesis approaches introduce different logic masking, which further results in different fault rate. Here we present the area and yield rate for 18 synthesis results obtained by ABC for a typical MCNC benchmark, by assuming rate = 0.1%, clearly we can see synthesis affect yield rate in Y-diss, ….
However, existing synthesis doesn’t maximize yield rate explicitly.

9. How and Where to Place Logic Masking? — Our Major Contributions
Propose a Robust FPGA resynthesis (ROSE)
Maximize the stochastic yield rate for FPGAs
No need to locate faults
Use the same synthesis for different chips of one FPGA application
Proposed a new PLB template for robustness
ROSE + Robust Template reduces fault rate by 25% with 1% fewer LUTs, and increases MTBF by 31% while preserving the logic depth
compared to Berkeley ABC

10. Outline Background Preliminaries Robust Resynthesis
Experimental Results
Conclusion and Future Work

11. FPGA Synthesis Flow
Attempt to re-map a logic block by Boolean matching
Boolean matching can be used to handle both homogenous and heterogeneous PLBs

12. FPGA Synthesis Flow (cont.)
Multi-iterations of Boolean Matching-based Resynthesis
(Source: Andrew Ling, University of Toronto, DAC'05)

13. Boolean Matching for Resynthesis
2-LUT
2-LUT f
2-LUT
2-LUT g ?
2-LUT
Formulate the sub-problem of resynthesis to Boolean matching (BM)
BM: Can function f be implemented in circuit g ?
Resynthesis: Is there a configuration to g so that for all inputs to g, f is equivalent to g?
Existing algorithms: area/delay-optimal
(Source: Andrew Ling, University of Toronto, DAC'05)

14. Outline Background Preliminaries Robust Resynthesis
Problem Formulation
FTBM Algorithm
Robust PLB Template
Experimental Results
Conclusion and Future Work

15. Modeling of Faults
Model both faults in LUT configurations and the faults in intermediate wires as random variables, whose probabilities are given as inputs of our problem.

16. ROSE: Robust Resynthesis w/ FTBM
Boolean Matching
Inputs
PLB H and Boolean function F
Fault rates for the inputs and the SRAM bits of the PLB
Outputs
Either that F cannot be implemented by PLB H
Or the configuration of H which minimizes the probability that the faults are observable in the output of the PLB under all input vectors.
FTBM tasks breakdown:
Step 1: Find a Boolean matching solution
Step 2: Evaluation the stochastic fault rate of a solution
Fault-Tolerant Boolean Matching

17. FTBM Step1: SAT Encoding for FTBM
Conjunctive Normal Form (CNF)
If implementable, multiple configurations might exist
The one with minimal fault rate is needed!

18. FTBM Step2: Fault Rate Calculation Based on SSAT
Simulation-based fault rate calculation
Not scalable for multiple defects
SAT-based fault rate calculation
Intelligently modeling random defects
Deterministic SAT vs. SSAT
Stochastic SAT
Deterministic SAT

19. SSAT Encoding for Fault Rate Calculation
GUI Version 1
Binary search is performed to find the maximal β
Faults in intermediate wires
Faults in LUT configurations

20. Example: SAT-Based FTBM
g= !x1!x3+ !x2
abc g
000 1
001
010
011
100
101
110
111
Boolean matching
PLB Template
Boolean function

21. Example: SAT-Based FTBM Step1: CNFs for the PLB template
G LUT = ( x x2+ ¬L0 + z) ( x x2+ L0 + ¬ z)
( x1 + ¬ x2+ ¬L1 + z) ( x1 + ¬ x2+ L1 + ¬ z)
(¬ x x2+ ¬L2 + z) (¬ x x2+ L2 + ¬ z)
(¬ x1 + ¬ x2+ ¬L3 + z) (¬ x1 + ¬ x2+ L3 + ¬ z)
PLB Characteristic Function: G = G LUT1 · G LUT2 · G LUT3

22. Example: SAT-Based FTBM Step2: Replication based on Truth Table
G = G LUT1 · G LUT2 · G LUT3
abc g
000 1
001
010
011
100
101
110
111
Replication
SAT Instance:
G expand = G[X/000, f/1, z/z0] · G[X/001, f/1, z/z1]
G[X/010, f/1, z/z2] · G[X/011, f/0, z/z3]
G[X/100, f/1, z/z4] · G[X/101, f/1, z/z5]
G[X/110, f/0, z/z6] · G[X/111, f/0, z/z7]

23. Example: SAT-Based FTBM Step3: SAT Solving and Mapping
SAT Instance:
G expand = G[X/000, f/1, z/z0] · G[X/001, f/1, z/z1]
G[X/010, f/1, z/z2] · G[X/011, f/0, z/z3]
G[X/100, f/1, z/z4] · G[X/101, f/1, z/z5]
G[X/110, f/0, z/z6] · G[X/111, f/0, z/z7]
SAT!
Returned SAT assignments: L1(00) = 0, L1(01)=0, L1(10)=0, L1(11)=1, …

24. Example: SAT-Based FTBM Step4: Exploring More SAT Solutions
Augmented SAT Instance:
G expand = G[X/000, f/1, z/z0] · G[X/001, f/1, z/z1]
G[X/010, f/1, z/z2] · G[X/011, f/0, z/z3]
G[X/100, f/1, z/z4] · G[X/101, f/1, z/z5]
G[X/110, f/0, z/z6] · G[X/111, f/0, z/z7]
¬ (L1(00) = 0, L1(01)=0, L1(10)=0, L1(11)=1, …)
/* Complement of previous SAT assignments */
Fault rate = 0.2
Fault rate = 0.3
New Configuration
Previous Configuration

25. PLB Templates for SAT-based Resynthesis
Area efficient templates [A. Ling, DAC’05]
Proposed robust template w/ path-reconvergence
Can be configured by existing FPGAs

26. Templates for SAT-based Resynthesis (cont.)
Robust PLB template introduces more potential of don’t-cares
ROSE maximizes don’t-cares iteratively at each template output
Observability don’t-care
Satisfiability don’t-care
I’s well known that path-reconver introduces more don’ts-cares, which can mask defects. Specifically, there are SAT-don’tcare and obs-don’t cares. ROSE tries to maximze do’t-cares iteratively at each template output. Observisly, it’s a heuristic, template and alg, two orthogonal, both can be improved in the future

27. Outline Background Preliminaries Robust Resynthesis
Experimental Results
Conclusion and Future Work

28. Experimental Settings
Implementation in OAGear
SAT-BM uses miniSAT2.0
QUIP benchmarks are tested
Are first mapped with 4-LUTs by Berkeley ABC
Resynthesis settings
One traversal is performed
Blocks with up to 10 inputs are considered
The fault rate of the chip is calculated by Monte Carlo simulation with 20K random vectors assuming the single fault
Results are verified by ABC equivalency checkers

29. Full-chip Fault Rate by Monte Carlo Simulation
Fault rate is the percentage of input vectors that cause observable output errors assuming the single fault.
>30% fault rate reduction!

30. ABC vs. ROSE/A vs. ROSE/R:
Area (LUT#)
ABC vs. ROSE/A vs. ROSE/R:
1: 0.9 : 0.99

31. Estimation of Mean Time Between Failure
SER modeling: [Mukherjee, HPCA, 2005]
Assume max-size FPGA: 330,000 LUTs
31% MTBF increase!
MTBF is imporant at system level, using the setting in the existing paper by assuming single defect, ….

32. Outline Background Preliminaries Robust Resynthesis
Experimental Results
Conclusion and Future Work

33. Conclusions and Future Work
Developed ROSE and a robust template.
ROSE is an orthogonal approach compared to existing fault-tolerant technique.
Virtually no overhead on power, delay and area
In the future, we will consider
Multiple correlated faults,
Alternative algorithms,
Extension to standard cell-based circuits,
Impacts on testability.
In this paper, we only consider single defect, but our algorithm can handle multiple defects, but can’t handle correlation between defects
On the synthesis algorith side, …
Related to architecture aspect, we will

34. Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching
Yu Hu, Zhe Feng, Rupak Majumdar and Lei He
University of California, Los Angeles