1. Working groups status report on Feedbacks
A.Drago, K.Bertsche
SuperB Meeting 
 26-30 January 2000
SLAC

2. Main Topics
SuperB parameters
Subsystem main list
R & D
Conclusion

3. 4ey , 2Nb LER/HER Unit June 2008 Jan. 2009 2Nb, Ib/Ö2 E+/E- GeV 4/7 L
cm-2 s-1
1x1036
I+/I-
Amp
1.85 /1.85
2.00/2.00
2.82/2.82
4.00/4.00
Npart
x1010
5.52 /5.52
5.97/5.97
4.23/4.23
Nbun
1250
2500
Ibunch mA
1.48
1.6
1.13
q/2
mrad 25 30
bx* mm
35/20
by*
0.22 /0.39
0.21 /0.37 ex nm
2.8/1.6 ey pm
7/4
28/16 sx
9.9/5.7 sy
39/39
38/38
76/76 sz
5/5 xx
X tune shift
0.0043/0.0025
0.0046/0.0027
0.0032/0.0019
0.0092/0.0054 xy
Y tune shift
0.15 /0.15
0.128/0.128
0.090/0.090
0.064/0.064
RF stations
5/6
5/8
7/11
RF wall plug power MW
16.2 18
25.5
39.3
Total wall plug power

4. Machine parameters
The SuperB machine parameters must be finalized before we can finalize the feedback systems, in particular:
Harmonic number to design b-b-b feedbacks
Bunch / beam current to dimension power and number of feedback systems: this also affects machine impedance (see Krasnyck’ talk)
Transverse / longitudinal damping time (same goal)
Beam vertical emittance to study the impact of feedback system

5. Subsystem main list B-b-b longitudinal feedback
B-b-b transverse feedback
Dither feedback
Fast IP feedback
Low level RF
Longitudinal Bunch Position Control
1D or 2D bunch-by-bunch diagnostics

6. R & D Bunch by bunch longitudinal feedback
- the present system is based on very old DSP (digital signal processor) that are completely obsolete
- a new version (the so called G-Proto or iGp) is based on a FPGA (V-II) that is ~10 years old, it will become obsolete in 2/3 year
-a new design is necessary based on last version FPGA
- the digital processing unit design is in progress, the system will work at 12/16 bits to have a better dynamic range respect to the old 8 bit systems
- the analog front end/back end needs to be re-designed as well for compatibility with digital and due to the obsolescence of some parts
- kicker (cavity) and amplifiers are probably ok, but it should be evaluated for working with bunch pattern by 1 (i.e. ~2ns pulse)

7. R & D Bunch by bunch transverse feedback
- for best use of resources, the digital processing unit should use the same design as the longitudinal unit
- attention should be given to the kicker design to maintain low ring impedance in case of multiple feedback installation
- kicker response must be adapt for 2ns pulse (bunch space by 1)

8. R & D
Dither feedback
Dither in x, y, and (probably) y’, similar to existing system
Upgrades to existing system:
Dither at 1-3 kHz
More efficient coil designs to allow lower currents and smaller drivers
Fast corrections (above ~1 Hz) through dither system
Slow corrections (below ~1 Hz) through standard correctors

9. R & D
Fast IP feedback
- it can be implemented in parallel to the dither feedback (in particular on the vertical plane)
- it is independent from the transverse feedback but it uses identical hardware with different firmware/software
- it can be used bunch by bunch
- sensitivity and signal/noise are open questions  need tests and simulations
- it is not clear if the kicker should be identical the transverse kicker or different

10. R & D Low level RF necessary
opinion of the experts (Dan Van Winkle / Claudio Rivetta) is that it will soon be obsolete and must be redone using newer FPGAs
needs a Matlab simulator that should be upgraded for the SuperB parameters (C.Rivetta)
new design should be done by experts: e.g. the J.Fox team at SLAC or outsourced to Dimtel (D.Teytelman)

11. R & D Longitudinal Bunch Position Control - same as LLRF
- Claudio Rivetta has good know how and a good simulator

12. R & D 1D or 2D bunch-by-bunch diagnostics
Diagnostics in 1D or 2D, bunch-by-bunch and turn-by-turn, seems necessary for colliding two beams with so small vertical emittance and sigma
Without valid real time tools, it could be impossible to evaluate the wasting of luminosity along the bunch train

13. Conclusions
We have considered a list of subsystem with similar technological characteristics or with similar goals
All systems need at least some redesign
Unify the technological choices can help to request less design manpower and to simplify the system management