1. Fast monitoring of ROC analog currents
Kai Schweda (GSI/ U Heidelberg)
Venelin Angelov , Steffen Brucker, Gunnar Föhner, Esteban Rubio, Frank Schumacher, Stephan Siebig 14-Sep-2016

2. Current-peak monitoring for TRD in CR4
Run 1, occasionally major trips in gaseous detectors
Take snapshot of current peaks
4096 time-bins
Readout rate up to 1 MhHz
144 hv channels (out of 521)
Feb 2016, installed during TS1
No measurable noise
Adapt for TPC upgrade
Continuous readout at 1kHz
ISEG PS
Current peak detection system

3. Current sense (front end FE) board
x8 channels
leakage current
RISO 8x
SPI
EXT
FLASH
HV+ HV LV
FPGA
optional
4Mx
1|16
ISO7841DWW
10-15 mW
Input protection, Amplifier, Filter, Digitizer Delta-Sigma ADC AD7124-4
SPI
LVDS TX
SPI
LVDS 3
LVDS RX
VCC
VReg
HV-
BLVDS
CLK &
SYNC
~12 V
50 Hz
VREF
Ref
FPGA firmware update via UART
Dual configuration (built in and external flash)
User flash memory in FPGA
Readout rate up to 1 MHz
Digital isolators and Trafo specified for continuous usage at 2.8 kV.
Measure current by voltage at shunt resistor
Insulate HV from LV part ISO7841
Minimize 50Hz noise from LV power transformer/coils
Filter 30kHz noise from HV generator analogue filter

4. Man-power at PI Heidelberg
Front end card
Venelin Angelov (engineer/developer, head)
Steffen Brucker (developer/procurement)
Gunnar Föhner (engineer)
Backplane
Stephan Siebig (electrician/assembly)
Controller card
Esteban Rubio (engineer/developer)
Mechanical construction, power supply
Frank Schumacher (electrician/assembly)

5. Collaboration with other institutes
HD development and assembly
FRA performance in lab w/ ion sources
UNAM integration into data stream via elink to DAQ GBTX
performance tests in HD, FRA and PS/SPS testbeam
Zagreb performance tests in HD, FRA and PS/SPS testbeam (?)

6. Schedule Total cost 20k Euro
Now evaluation boards in operation key components under scrutiny (noise, long-term stability) - Digital Isolator ISO Delta-Sigma ADC AD Lattice XO2 FPGA
Feb channel-prototype card with USB readout/laptop noise tests in FRA lab with ion sources
May 2017 SPS/PS teastbeam with full stack P2 installation in CR4 with individual GEM chambers in pit
Jul 2017 final design of cards procurement of components hv supply: choose vendor, ISEG vs CAEN
Dec 2017 full system assembled and ready for installation in CR4

7. backup

8. Current sense (front end FE) board – (2) FPGA
debug port 2 Mb/s
backplane
CLK tx rx
Addr[14:0]
Addr[14:0]
Flash
Memory
Dat[7:0]
Dat[7:0]
Config
backplane rx
UART
Addr[6:0]
Dat[7:0] rd
DAC rd
2 Mb/s
Wishbone
rd/wr wr tx wr
2 Mb/s
run/config
SCLK
ADC_data
ADC
Data
Formatting
CSn
ADC
SPI
Adc_valid
Digital isolators
Serializer tx
backplane
SDO
DAC 8
SDI 8
SPI
8|12 channels x 32 bits/sample = 256|384 bits/sample
1 kS => 256|384 kbits/s
In config/debug mode: UART with 2 Mbits/s
Event buffer for debugging (8|12 channels x 512 samples x 32 bits)
More (8k) with external RAM installed
In run mode: send permanently very small header and ADC data from one sample, 8 channels, then send idle
Lattice XO2 Family
(TQFP144, 8k LE and 240 kBits RAM)
used in ALICE TRD HV current monitoring

9. Current sense front end (FE) board (3)

10. Control board -6V unregulated Trenz Electronic TE0720 (250 Eur)
backplane
100 KSamples x 32-Bits x 8 channels/FE = 25,6 Mbps x 9 FE = 230,4 Mbps = 28,8 MBps
+5V Power
Regulator
I, T mon
+6V unregulated
PL firmware update via USB or Ethernet.
Zynq running with Linux
-5V Power
Regulator
I, T mon
-6V unregulated
Trenz Electronic TE0720
(250 Eur)
ADC
Temp,
Humidity
USB connector
USB2
Xilinx Zynq
LVDS_TX 9
DDR3
ARM 9
dual core
Programable
Logic 9
LVDS_RX 2
RJ45 connector
1Gb Eth
LVDS_CLK
uSD connector
USD card
UART
OSC
LCD DISPLAY
1 x RJ45 with LVDS I/O
2 x LEMO TTL/NIM I/O
Shutdown 12V AC
I2C
ADC: Imon,
Tmon
Tsensor
1 x LEMO SYS_CLK
1 x LEMO SYNC
1 x RJ45 with SLVDS
E-Link ( 3 Diff pairs) 10