1. CS/EE 217 – GPU Architecture and Parallel Programming
Introduction
Daniel Wong, Assistant Professor
Department of Electrical and Computer Engineering
Cooperating Faculty, Department of Computer Science and Engineering

2. Welcome!

3. I’m stuck in California . . . 
About me
Born and raised in East Los Angeles
University of Southern California, Los Angeles, CA
BS Computer Engineering/Computer Science ‘09
MS Electrical Engineering ‘11
PhD Electrical Engineering ’15
Research Interest
Energy Efficient Computer Systems
GPGPUs, Data Centers, NVM Memories
Industry Experience
Samsung Semiconductor, Inc., San Jose, CA
Lawrence Livermore National Labs, Livermore, CA
I’m stuck in California 

4. Course Goals Learn how to program GPGPU processors and achieve
high performance
functionality and maintainability
scalability across future generations
Technical subjects
principles and patterns of parallel algorithms
processor architecture features and constraints
programming API, tools and techniques

5. Logistics Course Website Assignments/Projects Discussion/Help
Check often for announcements
Assignments/Projects
iLearn (iLearn.ucr.edu)
Discussion/Help
Piazza (

6. Textbook
D. Kirk and W. Hwu, “Programming Massively Parallel Processors – A Hands-on Approach, Second Edition”
CUDA by example, Sanders and Kandrot
Nvidia CUDA C Programming Guide

7. Attendance/Grading Attendance Grade Breakdown
You are expected to attend all lectures.
Some slides only make sense in lecture.
Grade Breakdown
Labs: 35%
Exam and Final: 45%
Project: 30%
Class Participation/Extra Credit: 5%

8. Lab Policies 3 slip days 15% penalty per late day
If it’s one minute late, it’s still late
No extensions will be given
All labs/projects are due at the end of the due date (midnight)
Projects should be uploaded to iLearn

9. Team Projects
Work can be divided up between team members in any way that works for you
However, each team member will demo the final checkpoint of each project individually, and will get a separate demo grade
This will include questions on the entire design
Rationale: if you don’t know enough about the whole design to answer questions on it, you aren’t involved enough in the project

10. Contact Instructor: Daniel Wong TA: AmirAli Abdolrashidi
Homepage:
Office: WCH 425
Office Hours: TBD
TA: AmirAli Abdolrashidi