1. The Data Handling Hybrid
TUM Physics Department E18
I.Konorov

2. Workshop PXD-DAQ I.Konorov
Overview
DHH functionality
SODA -Time Distribution system for PANDA
DHH design
22-d April 2010
Workshop PXD-DAQ I.Konorov

3. Workshop PXD-DAQ I.Konorov
DHH functionality
Voltage regulators
Slow control:
Provision of JTAG interface to configure PXD
Provision of slow control interface to configure DHH cards
Monitoring voltages, currents, temperature
CLOCK synthesis from COMMON clock and distribution
DAQ functionality
Synchronous distribution of TRIGGER, RESET(?), … signals
Data buffering : 4x1Gb/sec
Sub event building : merging 4 data blocks into one
Transmission of merged data to DAQ via high speed optical serial link
22-d April 2010
Workshop PXD-DAQ I.Konorov

4. SODA –PANDA time distribution system
Passive splitter
1x8, 1x16
SODA
controller
SODA
receiver
Multiplexer/
Data Concentrator
MHz
Reset
Burst
Start/Stop
HESR
PCI-e
SODA controller :
Provision of MHz reference clock, 10ppm or better
Provision of RESET, Burst, SuperBurst, Start/Stop
PC interface for configuration and status information
Lattice FPGA with SERDES
Optical splitter :
1x8; 1x16; 1x32
SODA receiver:
Mounted directly on Data Concentrator/Multiplexer module
MHz
RESET, SOB, EOB, Start/Stop
April Rauischholzhausen
PANDA DAQT & FEE WS

5. SODA interface K28.7 K28.7 K28.7 K28.7 K28.7 10 bits ECC(5b) K28.7
8/10 bit encoding
Command(packet) transmission/handshake
IDLE status
Synchronous command:
RESET, SOB, EOB, SuperBurst, Start, Stop, Trigger, 3 spare bits
Asynchronous commands
K28.7
K28.7
K28.7
K28.7
K28.7
10 bits
ECC(5b)
K28.7
K28.7 1
8 bits
ECC(7b)
K28.7
K28.7
K28.7
April Rauischholzhausen
PANDA DAQT & FEE WS

6. Workshop PXD-DAQ I.Konorov
DHH card design
DHH design based on commercial components :
FPGA(Lattice/Xilinx)
Optical transceivers
to DAQ
to DHH Controller
22-d April 2010
Workshop PXD-DAQ I.Konorov

7. DHH system architecture
DHH: optical network with one to all topology
DHH Controller
FPGA
Trigger
Clock
Belle
DAQ
Reset
Ready
PCIe
USB
VME
JTAG
22-d April 2010
Workshop PXD-DAQ I.Konorov

8. DHH – Trigger interface
Trigger provides:
Common clock
Trigger
Reset ?
Event number
DHH :
Busy/Ready ?
22-d April 2010
Workshop PXD-DAQ I.Konorov

9. Workshop PXD-DAQ I.Konorov
DHH-DAQ
Compute
Node
Compute
Node
22-d April 2010
Workshop PXD-DAQ I.Konorov

10. PXD-DHH-DAQ interface
4 copper serial links, 1Gb/s each
Aurora protocol, 8/10 bit encoding
One data block is one or more events
Average network bandwidth utilization – 80-90%
DHH => DAQ
4Gb/s or 2x3Gb/s
“Sub event” building
22-d April 2010
Workshop PXD-DAQ I.Konorov

11. Workshop PXD-DAQ I.Konorov
PXD frame timing
20 us readout time per frame
triggers
Rows
Frame N
Event M
Frame
N+1
Event
M+1
Frame
N+3
Event
M+2
Frame
N+4
Event
M+3 T
Rows
Frame
N+1
Event M
Frame
N+3
Event
M+1 T
22-d April 2010
Workshop PXD-DAQ I.Konorov

12. Workshop PXD-DAQ I.Konorov
List of questions
Common clock
frequency and stability
Trigger interface specification
Connector type
Signal levels
Trigger latency
Data flow control
Possible options:
Busy/Ready
Emulation of FEE capability
Data truncation
Event convolution
22-d April 2010
Workshop PXD-DAQ I.Konorov