Digital Electronics Tutorial: Sequential Logic

Digital Electronics Tutorial: Sequential Logic
Solutions ELEC1041 – Tut Sequential 1

Problem #1 In lecture, we presented an R-S latch based on cross-coupled NOR gates. It is also possible to construct an R’-S’ latch using cross-coupled NAND gates. (a) Draw the R’-S’ latch, labeling the R’ and S’ inputs and the Q and Q’ outputs. (b) Show the timing behavior across the four configurations of R’ and S’. Indicate on your timing diagram the behavior in entering and leaving the forbidden state when R’ = S’ = 0. (c) Draw the state diagram that shows the complete input/output and state transition behavior of the R’-S’ latch. (d) What is the characteristic equation of the R’-S’ latch. (e) Draw a simple schematic for a gated R-S latch with an extra enable input, using NAND gates only. ELEC1041 – Tut Sequential 2

Problem #1 Solution (1/5) (a) Draw the R-S latch, labeling the R and S inputs and the Q and Q outputs. Q S R ELEC1041 – Tut Sequential 3

Problem #1 Solution (2/5) (b) Show the timing behavior across the four configurations of R and S. Indicate on your timing diagram the behavior in entering and leaving the forbidden state when R=S=0. Q S R Forbidden Race Reset Hold Set Forbidden Reset Hold Set S R Q ELEC1041 – Tut Sequential 4

Problem #1 Solution (3/5) (c) Draw the state diagram that shows the complete input/output and state transition behavior of the R’-S’ latch. SR=01 SR=11 SR=10 SR=11 SR=01 Q Q 0 1 Q Q 1 0 Q Q 1 1 Q Q 0 0 SR=10 SR=01 SR=10 SR=10 SR=01 SR=00 SR=00 SR=00 possible oscillation between states 00 and 11 S'R'=11 SR=00 SR=11 ELEC1041 – Tut Sequential 5

characteristic equation
Problem #1 Solution (4/5) (d) What is the characteristic equation of the R-S latch. Break feedback path Q S R Q(t) Q(t+) R S S R Q(t) Q(t+) X X hold reset set not allowed X 1 0 0 1 0 Q(t) R S characteristic equation Q(t+) = S + R Q(t) ELEC1041 – Tut Sequential 6

Problem #1 Solution (5/5) Control when R and S inputs matter
(e) Draw a simple schematic for a gated R-S latch with an extra enable input, using NAND gates only. Q S R Control when R and S inputs matter The slightest glitch on R or S while enable is high could cause change in value stored R S Enable Q ELEC1041 – Tut Sequential 7

Problem #2 Consider a D-type storage element implemented in five different ways: (a) D-latch (i.e., D wired to the S-input and D’ wired to the R-input of an R-S latch); (b) Clock Enabled D-latch; (c) Master-Slave Clock Enabled D-Flip-flop; (d) Positive Edge-triggered Flip-flop; (e) Negative Edge-triggered Flip-flop; Complete the following timing charts indicating the behavior of these alternative storage elements. You can ignore set-up and hold time limitations (assume all constraints are meant): ELEC1041 – Tut Sequential 8

Problem #2 Solution (1) output from D-latch changes as D changes regardless of the clock. (2) output from clocked D-latch changes as D does only when the clock is high. (3) output from D M/S FF are the samples taken from the input at the falling edge of the clock. (4) output from positive edge FF changes relative to D at the rising edge of the clock. (5) output form negative edge FF are the samples taken from the input at the falling edge of the clock (same as part 3). ELEC1041 – Tut Sequential 9

Complete the timing diagram for this circuit.
Problem #3 Complete the timing diagram for this circuit. ELEC1041 – Tut Sequential 10

Complete the timing diagram for this circuit.
Problem #3 Solution Complete the timing diagram for this circuit. Toggles when T = 1 at the rising edge of the clock ELEC1041 – Tut Sequential 11

Problem #4 Design a 4 bit counter that counts through the sequence 0111, 1000, 1001, 1010, 1011, 1100, 1101 ELEC1041 – Tut Sequential 12

Problem #4 Solution Design a 4 bit counter that counts through the sequence 0111, 1000, 1001, 1010, 1011, 1100, 1101 "1" "0" “1" “1" “1" EN D C B A LOAD CLK CLR RCO QD QC QB QA ELEC1041 – Tut Sequential 13

Discuss all timing constraint in your design
Problem #5 You as a designer at XILION Micro Devices, have been asked to redesign part of your system to run at double the clock frequency. However, to maintain the compatibility with other parts of the system you like to keep the same clock frequency. What would you do to impress your Boss? Discuss all timing constraint in your design ELEC1041 – Tut Sequential 14

Problem #5 Solution One way is to double of the clock frequency locally, or put it in another way make your flip flop to be both positive and negative edged triggered. B CLOCK Flip flop sample on both edges CLOCK B CLK Conditions: Clk period 1. High Width of “CLK” should be larger than that required by the Flip Flop This can be controlled by the number of invertors (odd) before the XNOR gate. 2. Period of “CLK” should be larger than the (set up time + propagation Delay) of flip flop. ELEC1041 – Tut Sequential 15

Problem #6 Complete the count sequence table for the following shift register circuit. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 ELEC1041 – Tut Sequential 16

Problem #6 Solution Complete the count sequence table for the following shift register circuit. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 1 1 1 1 1 1 1 1 ELEC1041 – Tut Sequential 17

Problem #7 Consider the counter x74_163 from the xilinx library. Complete the timing diagram Below: (Note: LOAD and CLR are active low. P & T should be high to enable the counter P 163 T RCO CLK D QD C QC B QB A QA LOAD CLR ELEC1041 – Tut Sequential 18

Problem #7 Solution Indicates Undefined Clear Load P & T should be
High to enable count ELEC1041 – Tut Sequential 19

Problem #8 Design the logic for a 3-bit counter that follows the following sequence: 000, 111, 001, 110, 010, 101, 011, 100, 000 and repeats. Design the counter so when Reset is asserted, the counter enters the state 000. ELEC1041 – Tut Sequential 20

Problem #8 Solution (1/2) Design the logic for a 3-bit counter that follows the following sequence: 000, 111, 001, 110, 010, 101, 011, 100, 000 and repeats. Design the counter so when Reset is asserted, the counter enters the state 000. ELEC1041 – Tut Sequential 21

Problem #8 Solution (2/2) ELEC1041 – Tut Sequential 22

Problem #9 Design the logic for a 3-bit counter that follows the following sequence: 001, 010, 100, 101, 110, 001, and repeat. Design the counter so that it is self-starting, i.e., whatever state it comes up in, it will eventually get into the sequence as shown above. ELEC1041 – Tut Sequential 23

Problem #9 Solution 000 111 001 010 011 100 101 110 + + + Q2 Q1 Q0 1
1 Q2 = Q2 Q1 + Q2Q1 + Q0 = Q1 Q0 + Q2Q1 + Q1 = Q1 Q0 + ELEC1041 – Tut Sequential 24

Problem #10 Consider 3 bit Johnson Counter below. Derive it state transition table and diagrams ELEC1041 – Tut Sequential 25

Problem #10 Solution Q2Q1Q0 Q2Q1Q0 000 111 0 0 0 0 0 1 0 0 1 0 1 1
+ + + Q2Q1Q0 000 111 001 110 010 101 011 100 ELEC1041 – Tut Sequential 26

Problem #11 ELEC1041 – Tut Sequential 27

Problem #11 Solution (2/2) D1 D0 q0 X q1 Z 1 0 0 1 0 x 1 x 0 0
1 0 0 1 0 x 1 x X q1 q0 D0 0 0 D1 Z ELEC1041 – Tut Sequential 29

Problem #12 Solution (3/3) q2 D2 D1 0 0 x 1 0 0 x 0 1 0 x x 0 0 x x
Z ELEC1041 – Tut Sequential 33

Finite String Pattern Recognizer
Problem #13 Finite String Pattern Recognizer A finite string recognizer has one input (X) and one output (Z). The output is asserted whenever the input sequence …010… has been observed, as long as the sequence 100 has never been seen. Step 1. Understanding the problem statement Sample input/output behavior: X: … Z: … X: … Z: … ELEC1041 – Tut Sequential 34

Problem #13 Solution (1/5) S0 [0] S1 S2 S3 [1] S4 S5 S6 Reset 1 0,1
Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100. Outputs 1 Loops in State S0 [0] S1 S2 S3 [1] S4 S5 S6 Reset 1 0,1 Moore State Diagram Reset signal places FSM in S0 ELEC1041 – Tut Sequential 35

Problem #13 Solution (2/5) Exit conditions from state S3: have recognized …010 if next input is 0 then have …0100! if next input is 1 then have …0101 = …01 (state S2) S0 [0] S1 S2 S3 [1] S4 S5 S6 Reset 1 0,1 ELEC1041 – Tut Sequential 36

Problem #13 Solution (3/5) Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0 Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1 S0 [0] S1 S2 S3 [1] S4 S5 S6 Reset 1 0,1 ELEC1041 – Tut Sequential 37

Problem #13 Solution (4/5) 1 0,1 S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case! S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case! Reset S0 [0] 1 0,1 S1 S4 [0] [0] Final State Diagram S2 S5 [0] [0] S3 S6 [1] [0] ELEC1041 – Tut Sequential 38

Problem #13 Solution (5/5) Finite String Recognizer Review of Process:
• Write down sample inputs and outputs to understand specification • Write down sequences of states and transitions for the sequences to be recognized • Add missing transitions; reuse states as much as possible • Verify I/O behavior of your state diagram to insure it functions like the specification ELEC1041 – Tut Sequential 39

Finite String Pattern Recognizer
Problem #14 Finite String Pattern Recognizer A finite string recognizer has one input (X) and two output (Z1 & Z2). The output Z1 is asserted whenever the input sequence …010… has been observed, as long as the sequence 100 has never been seen. The output Z2 is asserted whenever the input sequence …100… has been observed Note that once Z2 = 1 has occurred, Z1 = 1 can never occur, but never vice versa Step 1. Understanding the problem statement Sample input/output behavior: X : … Z1: … Z2: … X : … Z1: … Z2: … ELEC1041 – Tut Sequential 40

Problem #14 Solution (1/8) S0 [00] S1 S2 S3 S4 S5 S6 Reset 1
Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100. Output Z1= 1 S0 [00] S1 S2 S3 [Z1=1] S4 S5 S6 [Z2=1] Reset Output Z2= 1 1 Moore State Diagram Reset signal places FSM in S0 ELEC1041 – Tut Sequential 41

Problem #14 Solution (2/8) Exit conditions from state S3: have recognized …010 if next input is 0 then have …0100! if next input is 1 then have …0101 = …01 (state S2) S0 [00] S1 S2 S3 [Z1=1] S4 S5 S6 [Z2=1] Reset 1 0 1 ELEC1041 – Tut Sequential 42

Problem #14 Solution (3/8) Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0 Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1 S0 [00] S1 S2 S3 [Z1=1] S4 S5 S6 [Z2=1] Reset 1 ELEC1041 – Tut Sequential 43

Problem #14 Solution (4/8) 1 S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case! S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case! Reset S0 [00] 1 S1 S4 [00] [00] S2 S5 [00] [00] S3 S6 [Z1=1] [Z2=1] ELEC1041 – Tut Sequential 44

Problem #14 Solution (5/8) S6 = …100; If next input is 1, then string could be prefix of (100)1(00) S4 handles just this case! BUT IS IT? Remember S3 should never be entered again, so S5 should be avoided Reset S0 [00] 1 S1 S4 [00] [00] Final State Diagram S2 S5 1 [00] [00] S3 S6 [Z1=1] [Z2=1] ELEC1041 – Tut Sequential 45

Problem #14 Solution (6/8) S6 = …100; If next input is 1, then string could be prefix of (100)1(00) Draw additional states for the string that must be recognized after S6 has been entered i.e. 100. Reset S0 [00] 1 S1 S4 [00] [00] S8 [00] S2 S5 [00] [00] S7 [00] 1 S3 S6 [Z1=1] [Z2=1] ELEC1041 – Tut Sequential 46

Problem #14 Solution (7/8) S6 = …100; If next input is 1, then string could be prefix of (100)1(00) Draw additional states for the string that must be recognized after S6 has been entered i.e. 100. Reset S0 [00] 1 S1 S4 [00] [00] S8 [00] S2 S5 [00] [00] S7 [00] 1 S3 S6 [Z1=1] [Z2=1] S9 [00] ELEC1041 – Tut Sequential 47

Problem #14 Solution (8/8) S6 = …100; If next input is 1, then string could be prefix of (100)1(00) Draw additional states for the string that must be recognized after S6 has been entered i.e. 100. Reset S0 [00] 1 S1 S4 [00] [00] S8 [00] S2 S5 1 [00] [00] S7 [00] 1 S3 S6 [Z1=1] [Z2=1] S9 [00] ELEC1041 – Tut Sequential 48

Problem #15 N + 2 converter A sequential network has one input X and two outputs S and V. X represent a four bit binary number N, which is input least significant bit first. S represents a four bit binary number equal to N + 2, which is output least significant bit first. At the time the fourth input is sampled, V = 1, in N + 2 is too large to be represented by four bits; otherwise V = 0. Derive a Mealy state graph and table with a minimum number of states ELEC1041 – Tut Sequential 49

Problem #15 Solution (1/3) FSM X S V S (N) (N +2) X 0 0000 0010 0
N3N2N1N0 S (N) (N +2) X FSM V Example: N +2 Serial Converter Assume numbers are +ve (0N15) Conversion Process Bits are presented in bit serial fashion starting with the least significant bit Single input X, Two output S, V ELEC1041 – Tut Sequential 50

Problem #15 Solution (ver 1) (2/3)
Reset S0 0/00, 1/10 S1 0/10 1/00 S2 S3 S4 S5 0/10, 1/01 Present State S0 S1 S2 S3 S4 S5 Next State Output SV X=0 X=1 00 10 01 ELEC1041 – Tut Sequential 51

ROM-based Implementation Truth Table/ROM I/Os 1 X Q2 Q1 Q0 ROM Address D2 D1 D0 ROM Outputs S V CLK 9 15 CLK QD 14 Z S 175 QD X converter ROM X V 13 D 10 QC 12 C 11 Q2 D2 5 QC Q1 D1 B 7 4 QB Q0 D0 A 6 QB 2 QA 1 1 CLR 3 QA \Reset Circuit Level Realization 74175 = 4 x positive edge triggered D FFs In ROM-based designs, no need to consider state assignment ELEC1041 – Tut Sequential 52

Controller Data path N3N2N1N0 + N0 Co S = A XOR B XOR Cin Co = AB + (A + B) Cin 1 Sc Sb FSM S1 S0 X Sb MUX A B S0 V Cin Co MUX 1 bit adder CoQ S1 S Sc CoD D Q CoQ Reset S0 [0,0] S2 [0,1] S3 S1 [1,0] Q1+ = Q1 XOR Q0 PS NS Outputs Q1Q Q1+ Q Sb Sc Q0+ = Q0 Sb = Q1 Q0 Sc = Q1 ELEC1041 – Tut Sequential 53

Q1+ = Q1 XOR Q0 Q0+ = Q0 Sb = Q1 Q0 Sc = Q1 A B 1 bit adder S Sb 1 MUX X CoQ Co Sc Cin D Q CoD V S0 S1 Q0 Q1 CLK ELEC1041 – Tut Sequential 54

Problem #16 N - 2 converter A sequential network has one input X and two outputs S and V. X represent a four bit binary number N, which is input least significant bit first. S represents a four bit binary number equal to N - 2, which is output least significant bit first. At the time the fourth input is sampled, V = 1, in N - 2 is too small to be represented by four bits; otherwise V = 0. Derive a Mealy state graph and table with a minimum number of states ELEC1041 – Tut Sequential 55

Problem #16 Solution (1/3) FSM X S V S (N) (N - 2) X 0 0000 1110 1
X S V N3N2N1N0 S X FSM V Example: N -2 Serial Converter Assume numbers are +ve (0N15) Conversion Process Bits are presented in bit serial fashion starting with the least significant bit Single input X, Two output S, V ELEC1041 – Tut Sequential 56

Present State S0 S1 S2 S3 S4 S5 Next State Output SV X=0 X=1 00 10 11 Reset S0 0/00, 1/10 S1 0/10 1/00 S2 S3 S4 0/11, S5 ELEC1041 – Tut Sequential 57

ROM-based Implementation ROM Address ROM Outputs X Q2 Q1 Q0 S V D2 D1 D0 1 1 1 1 CLK 9 15 1 1 1 CLK QD 14 1 1 175 1 1 1 X converter ROM S QD 13 D 10 1 1 1 X V QC D2 12 C 11 Q2 1 1 5 QC Q1 D1 B 7 1 1 X X X X X 4 QB Q0 D0 A 6 1 1 1 X X X X X QB 2 1 1 1 QA 1 1 CLR 3 1 1 1 1 QA \Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Circuit Level Realization 74175 = 4 x positive edge triggered D FFs 1 1 1 X X X X X 1 1 1 1 X X X X X Truth Table/ROM I/Os In ROM-based designs, no need to consider state assignment ELEC1041 – Tut Sequential 58

Controller Data path Bo S = A XOR B XOR Bin Bo = A’B + (A’ + B) Bin 1 Sc Sb FSM N3N2N1N0 - X0 S1 S0 X Sb MUX A B S0 V Bin Bo MUX 1 bit subtractor BoQ S1 S Sc CoD D Q BoQ Reset S0 [0,0] S2 [0,1] S3 S1 [1,0] Q1+ = Q1 XOR Q0 PS NS Outputs Q1Q Q1+ Q Sb Sc Q0+ = Q0 Sb = Q1 Q0 Sc = Q1 ELEC1041 – Tut Sequential 59

Q1+ = Q1 XOR Q0 Q0+ = Q0 Sb = Q1 Q0 Sc = Q1 A B 1 bit subtractor S Sb 1 MUX X CoQ Co Sc Cin D Q CoD V S0 S1 Q0 Q1 CLK ELEC1041 – Tut Sequential 60

Problem #17 Solution version 1 (1/4)
ELEC1041 – Tut Sequential 62

+ ELEC1041 – Tut Sequential 63

+ + + + ELEC1041 – Tut Sequential 64

1 0 1 1 0 0 q1 D0 0 0 1 1 1 0 q1 D1 0 0 0 1 1 0 q1 D2 0 x 1 1 1 x q1 Z ELEC1041 – Tut Sequential 65

ELEC1041 – Tut Sequential 66

+ We relax the requirement for undefined states to Go to zero, however, we still require them to go to a valid state ELEC1041 – Tut Sequential 67

+ + ELEC1041 – Tut Sequential 68

1 1 0 0 x 0 x x q1 D0 0 1 1 0 x 0 x x q1 D1 0 0 0 1 x 0 x x q1 D2 0 1 1 1 x 0 x x q1 D1 ELEC1041 – Tut Sequential 69

1 1 0 0 x 0 x x q1 D0 0 1 1 0 x 0 x x q1 D1 + 0 1 1 1 x 0 x x q1 D1 0 0 0 1 x 0 x x q1 D2 101 010 110 010 111 100 undefined states end uo in valid states ELEC1041 – Tut Sequential 70

Problem #18 Consider the design of a sequence detector finite state machine that will assert a 1 when the current input equals the just previously seen input. (a) Draw as simple state diagrams for a MEALY MACHINE and a MOORE MACHINE implementation as you can (minimization is not necessary). The MEALY MACHINE should have fewer states. Briefly explain why. (b) If the Mealy Machine is implemented as a SYNCHRONOUS MEALY MACHINE, draw the timing diagram for the example input/output sequence described above. (c) If the timing behaviors are different for the MOORE, MEALY, and SYNCHRONOUS MEALY machines, explain the reason why. ELEC1041 – Tut Sequential 71

Problem #18 Solution(1/4) Sample input/output sequence: ELEC1041 – Tut Sequential 72

Problem #18 Solution(2/4) 0/1 S1 0/0 S1 S0 S0 [0] 1/0 1 S2 S2 S4 [1]
(a) Draw as simple state diagrams for a MEALY MACHINE and a MOORE MACHINE implementation as you can (minimization is not necessary). The MEALY MACHINE should have fewer states. Briefly explain why. S0 S1 S2 0/0 1/0 0/1 1/1 Mealy S0 [0] 1 S1 S2 S4 [1] Moor Since the output of Mealy Machines depend on both the current state and the current input, they don’t need as many states to represent input/output combinations. ELEC1041 – Tut Sequential 73

Problem #18 Solution(3/4) (b) If the Mealy Machine is implemented as a SYNCHRONOUS MEALY MACHINE, draw the timing diagram for the example input/output sequence described above. ELEC1041 – Tut Sequential 74

Problem #18 Solution(4/4) S0 S1 S2 0/0 1/0 0/1 1/1
(c) If the timing behaviors are different for the MOORE, MEALY, and SYNCHRONOUS MEALY machines, explain the reason why. S0 S1 S2 0/0 1/0 0/1 1/1 The timing behaviors of a Moore Machine and a Synchronous Mealy Machine are the same. The Mealy Machine will behave differently because the output changes as soon as the input changes rather than at the next clock cycle. S1 S0 S2 ELEC1041 – Tut Sequential 75

Problem #19 Consider a 3-bit counter that behaves as follows. The counter has a mode input M. When M is true, the counter counts in the sequence 0, 2, 4, 6, 1, 3, 5, 7, 0 and repeat. When M is false, the counter counts in the sequence 0, 1, 6, 7, 2, 3, 4, 5, 0 and repeat. The M input can change at anytime to cause the counter to change into either mode. (a) Complete the Encoded STATE TRANSITION TABLE for this counter. (b) Use the K-maps below to find the minimized two-level implementation of the counter’s next state functions. ELEC1041 – Tut Sequential 76

Problem #19 Solution (1/4) (a) Complete the Encoded STATE TRANSITION TABLE for this counter. M = 0: 0, 1, 6, 7, 2, 3, 4, 5, 0 and repeat M = 1: 0, 2, 4, 6, 1, 3, 5, 7, 0 and repeat ELEC1041 – Tut Sequential 77

M’ Q0’ Q2 + M Q1 Q2’ + M’ Q0 Q2’ + M Q1’ Q2
Problem #19 Solution (2/4) (b) Use the K-maps below to find the minimized two-level implementation of the counter’s next state functions. D2 M’ Q0’ Q2 + M Q1 Q2’ + M’ Q0 Q2’ + M Q1’ Q2 ELEC1041 – Tut Sequential 78

M Q1’ + Q0 Q1’ Q2’ + M’ Q1 Q2 + M’ Q0’ Q1
Problem #19 Solution (3/4) (b) Use the K-maps below to find the minimized two-level implementation of the counter’s next state functions. D1 M Q1’ + Q0 Q1’ Q2’ + M’ Q1 Q2 + M’ Q0’ Q1 ELEC1041 – Tut Sequential 79

Problem #19 Solution (4/4) D0 M’Q0’ + Q0’ Q1 Q2 + M Q0 Q2’ + M Q0 Q1’
(b) Use the K-maps below to find the minimized two-level implementation of the counter’s next state functions. D0 M’Q0’ + Q0’ Q1 Q2 + M Q0 Q2’ + M Q0 Q1’ ELEC1041 – Tut Sequential 80

Figure below illustrates the use a Single-Pole Single-Throw
Problem #20 Figure below illustrates the use a Single-Pole Single-Throw (SPST) switch to increment the count value in the counter. Every throw of the switch causes a low-to-high transition on the clock input (CLK) which in turn causes the counter to increment by 1. However, we have noticed that each throw of the switch causes multiple increments in the count value. Furthermore multiple increments are equal to each other and changes from one throw of the switch to the next. Explain Why? How to do rectify the problem + switch + P 163 T CLK RCO CLK D QD C QC B QB A QA LOAD ELEC1041 – Tut Sequential 81 CLR

This problem is due to bouncing effect in in a mechanical
Problem #20 Solution (1/2) This problem is due to bouncing effect in in a mechanical switch. The switch does not make a clean contact at-once. It bounces several times from its final position before coming to rest. This causes several low-to-high transition at the clk signal causing multiple count increments. Switch + clk Switch Clk ELEC1041 – Tut Sequential 82

b) This problem can be overcome by using a debouncing
Problem #20 Solution (2/2) b) This problem can be overcome by using a debouncing circuitry shown below. Here we use a Single-Pole Double-Throw (SPDT) switch to increment the count value in the counter. In spite of mechanical switch making several contacts, since the switch after the throw to one position never bounces back all the way to the opposite position the S-R latch will either be in set or hold state and its clk output stays constant after the first transition. + Initial position clk /switch switch /S /R switch \switch + clk Initial position ELEC1041 – Tut Sequential 83

Digital Electronics Tutorial: Sequential Logic

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