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Discussion Items Clock PC and/or VME CPU Trigger readout

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Presentation on theme: "Discussion Items Clock PC and/or VME CPU Trigger readout"— Presentation transcript:

1 Discussion Items Clock PC and/or VME CPU Trigger readout
Clock distribution Local clock PC and/or VME CPU Trigger readout ECL Belle2link

2 Clock [1] Who needs what clock? COPPER system: 42.3MHz
KEK has customized crystals. RocketIO (high speed link): 127MHz / 125MHz 127MHz crystal is not commercially available, which is needed if one tries to get that from local oscillator. Someone can distribute customized crystals. 5000 JPY/crystal. Switching off clocks / switching clock freq. to others. Onboard-implemented oscillator or pluggable clock card? FINESSE SCK & RCK (differential pairs).

3 Clock [2] Who (related to TRG) needs what clock?
GDL & CDC: MN and YI will discuss. ECL: through collector board(s). FAM on the detector through collector board 6x TMM in the EH through GDL (single-ended LEMO?). TOP: through RCK or else. 9 boards need clock. KLM: same as TOP for convenience.

4 Clock [3] Who (related to TRG) needs what clock?
All trigger sub-modules will use the clock from the single origin (or use a local oscillator during maintenance). Clock monitoring 2x pins should be implemented on the electronics board.

5 PC and/or VME CPU [1] # of PCs and/or VME CPUs
TTD: 10 CPUs. GDL+CDC-TRG: 5 CPUs. ECL: O(1) PCs to control 52 FAMs + >= 1 PC for firmware downloading. E-KLM: 6 PCs + 9 VME crates. CDC: >= 1 PC HV/LV control: >= 1 PC per detector Isolated network from “fbdaq”. CPUs are booted up from limited # of places.

6 PC and/or VME CPU [2] Slow control
Another isolated network from the one in the previous page.

7 Trigger Readout [1] TRG will be readout by B2Link?
Yes. Any possibility to recycle AMT-3 FINESSE? No. Summary needed Homework to YI by the next B2GM.

8 Trigger Readout [2] CDC TRG / ECL TRG raw data TOP TRG raw data
Readout by local monitoring system. Need not taken care by the CDAQ. TOP TRG raw data Readout by COPPERs.

9 Homework to MN Level-1 latency


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