1. Instruction Sets Chapter 2
Be able to explain the organization of the classical von Neumann machine and its major functional components.
Be able to demonstrate understanding of instruction set content including types of instructions, addressing modes, and instruction formats.
Master instruction execution.
Chapter 2

2. Instruction Set The repertoire of instructions of a computer
Different computers have different instruction sets
But with many aspects in common
Early computers had very simple instruction sets
Simplified implementation
Many modern computers also have simple instruction sets

3. Stored Program Concept
Instructions are bits
Programs are stored in memory — to be read or written just like data
4D2A 56B0 is stored at a location – how does one interpret this?
Processor
Memory
memory for data, instructions,
addresses, programs,
compilers, editors, etc.
Fetch & Execute Cycle
Instructions are fetched and put into a special register
Bits in the register "control" the subsequent actions
Operand fetch
Execute
Fetch the “next” instruction and continue

4. Registers vs. Memory
Arithmetic instructions operands must be registers, — only 32 registers provided
Register size – bigger the better?
Number of registers – more the better?
Compiler associates variables with registers
Control
Input
Datapath
Memory
Output
Registers
Functional
units
I/O
Processor

5. Compilation to execution - review
Higher Level Language
MIPS Assembly Language
Symbolic
More primitive than higher level languages e.g., no sophisticated control flow
Assembly can provide 'pseudoinstructions'
e.g., “move $t0, $t1” exists only in Assembly
would be implemented using “add $t0,$t1,$zero”
MIPS instructions
Very restrictive e.g., MIPS Arithmetic Instructions
Defined registers
Machine Language
When considering performance you should count real instructions
Design goals: maximize performance and minimize cost, reduce design time

6. MIPS arithmetic All instructions have 3 operands
Two inputs
One result
Operand order is fixed (destination first) Example: A = B + C If B is in $s1 and C is in $s2 then
MIPS code: add $s0, $s1, $s2
Result (A) is in $s0
If B and C are in main memory, then first load the memory contents to respective registers.
Compilers map variables to registers.

7. Arithmetic Example C code: Compiled MIPS code: f = (g + h) - (i + j);
add t0, g, h # temp t0 = g + h add t1, i, j # temp t1 = i + j sub f, t0, t1 # f = t0 - t1

8. Memory Operand Example 1
C code:
g = h + A[8];
g in $s1, h in $s2, base address of A in $s3
Compiled MIPS code:
Index 8 requires offset of 32
4 bytes per word
lw $t0, 32($s3) # load word add $s1, $s2, $t0
offset
base register

9. Memory Operand Example 2
C code:
A[12] = h + A[8];
h in $s2, base address of A in $s3
Compiled MIPS code:
Index 8 requires offset of 32
lw $t0, 32($s3) # load word add $t0, $s2, $t0 sw $t0, 48($s3) # store word

10. Logical Operations Instructions for bitwise manipulation
Java
MIPS
Shift left
<<
sll
Shift right
>>
>>>
srl
Bitwise AND
&
and, andi
Bitwise OR |
or, ori
Bitwise NOT ~
nor
Useful for extracting and inserting groups of bits in a word

11. Shift Operations op rs rt rd shamt funct
6 bits
5 bits
shamt: how many positions to shift
Shift left logical
Shift left and fill with 0 bits
sll by i bits multiplies by 2i
Shift right logical
Shift right and fill with 0 bits
srl by i bits divides by 2i (unsigned only)

12. Conditional Operations
Branch to a labeled instruction if a condition is true
Otherwise, continue sequentially
beq rs, rt, L1
if (rs == rt) branch to instruction labeled L1;
bne rs, rt, L1
if (rs != rt) branch to instruction labeled L1;
j L1
unconditional jump to instruction labeled L1
§2.7 Instructions for Making Decisions

13. Compiling If Statements
C code:
if (i==j) f = g+h; else f = g-h;
f, g, … in $s0, $s1, …
Compiled MIPS code:
bne $s3, $s4, Else add $s0, $s1, $s j Exit Else: sub $s0, $s1, $s2 Exit: …
Assembler calculates addresses

14. MIPS Registers – Names and Functions
Name Reg Function
Num
$zero constant 0
$at reserved for assembler
$v expression evaluation and results of a function
$v expression evaluation and results of a function
$a0-$a procedure arguments
$t0-$t to 15 temporary (not preserved across call – can be overwritten by callee)
$s0-$s to 23 saved temporary (preserved across call – saved/restored by callee)
$t8-$t temporary (not preserved across call)
$k reserved for OS kernel
$k reserved for OS kernel
$gp pointer to global area
$sp stack pointer
$fp frame pointer
$ra return address (used by function call)

15. Memory Organization 8 bits of data 1 2 3
Think of memory as a large, single-dimensional array.
Memory address is like index of the array.
Memory reference is at the byte level.
Retrieve a minimum of 1 byte from memory in each access.
The instructions are 4 bytes long. Does this require 4 accesses to memory?
8 bits of data 1 2 3 4 5 6 7 8

16. Memory Organization x x x x
Bytes are nice, but most data items use larger "words“. How many bits in an instruction?
For MIPS, a word is 32 bits or 4 bytes.
232 bytes with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8,
Words are aligned.
32 bits of data 4
32 bits of data
Registers hold 32 bits of data 8
32 bits of data 12
32 bits of data
... 00 01 10 11 4 8 12
What are the 2 LSBs (least significant bits) of a word address? x x x x

17. Categories of Instructions
Data manipulation
Arithmetic
Logical
Shift
Comparison
add, sub, addi
Data manipulation
Data transfer
Program Manipulation
Status Management
Program Manipulation
Unconditional and conditional branch
Subroutine / procedure calls
beq, bne, j, jal
Status Management
Exceptions
Interrupts
Software / Hardware
Interrupt processing vs procedure call
Data transfer
Memory transfer
Intra CPU
I/O
Stack
lw, sw
Instruction size
Variable
Fixed (MIPS)

18. Typical Instructions op rs rt rd shamt funct R I
Instruction Meaning Data Manipulation
add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 – $s3 Data Transfer
lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1 Program Manipulation
bne $s4,$s5,L Next instr. is at Label if $s4 = $s5 beq $s4,$s5,L Next instr. is at Label if $s4 = $s5
Formats: /
op rs rt rd shamt funct
op rs rt 16 bit address
op bit address R I J

19. To summarize:
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20. MIPS Addressing Modes
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21. MIPS Addressing Modes EA = Effective Address EA=PC+ (Address X 4)
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22. Von Neumman Architecture
Fetch
Execute
Decode
From Wikipedia

23. What are essential ingredients of an instruction?
Take as an example a very simple arithmetic computation
A = B + C
Definition of operation – op code
Address of A
Address of Result
Address of B
Address of Data Source
Address of C
Address of Next Instruction
Consider a very simple processor like 8080
8 bit word and 16 bit address
Size of the instruction?

24. MIPS Instruction Execution Cycle
Fetch
Decode
Operand
Execute
Result
Store
Next
Obtain instruction from program storage
Determine required actions and instruction size
Locate and obtain operand data
Compute result value or status
Deposit results in storage for later use
Determine successor instruction
Copyright 1997 UCB

25. Reducing Instruction Length – a few approaches
Program Counter contains address of next instruction
Make destination address implicit
Make source address implicit
Make source and destination address the same
Use register addressing rather than memory addressing
Use addressing modes
Short address in instruction
Access to large memory space
Step through array

26. Addressing Mode Examples
MIPS
Register Addressing
Base or displacement
Effective Address =
($n) + value in instruction
Immediate addressing
Operand in instruction
PC – relative
(PC) + value in instruction
Other Computers
Direct
Indirect
Immediate
Indexed
Relative
Register direct
Register indirect
Stack
Auto increment
Auto decrement

27. Guiding principles in instruction set selection
Make Common Case Fast
Smaller is faster
Simplicity favors regularity
Good design demands compromise

28. Procedure Calls Modern software design leads to many procedures
Procedures help in abstraction – detail hiding
Process
Procedure call
Put parameters in locations (maybe registers) accessible to the procedure
{Save registers that may change!!}
Transfer control
Perform the required task
Place parameters in place accessible to the main program
Return to the calling procedure
Nested procedures
How does this work
Need to transfer to new address
Save the “return” address
After procedure execution return to the old “return” address

29. Example 161 jal Proc_Addr Increment PC to point to next instruction
Save new PC in $ra (register 31)
Branch to Proc_Addr
Return achieved by
jr $31

30. Review Instruction set architecture Instruction set
Abstract interface between lowest level software and the hardware.
Lets programmers think in terms of functions rather than implementation.
Instruction set
Types of instructions.
Instruction formats.
Addressing modes.
Content analysis of instructions.
Instructions will be too long.
Reduce the size of the instruction.
An approach to motivate addressing modes and some hardware components.
Steps in executing an instruction
Execution of individual instructions.

31. Translation and Startup
Many compilers produce object modules directly
§2.12 Translating and Starting a Program
Static linking

32. Assembler Pseudoinstructions
Most assembler instructions represent machine instructions one-to-one
Pseudoinstructions: figments of the assembler’s imagination
move $t0, $t1 → add $t0, $zero, $t1
blt $t0, $t1, L → slt $at, $t0, $t1 bne $at, $zero, L
$at (register 1): assembler temporary

33. Producing an Object Module
Assembler (or compiler) translates program into machine instructions
Provides information for building a complete program from the pieces
Header: described contents of object module
Text segment: translated instructions
Static data segment: data allocated for the life of the program
Relocation info: for contents that depend on absolute location of loaded program
Symbol table: global definitions and external refs
Debug info: for associating with source code

34. Linking Object Modules
Produces an executable image
1. Merges segments
2. Resolve labels (determine their addresses)
3. Patch location-dependent and external refs
Could leave location dependencies for fixing by a relocating loader
But with virtual memory, no need to do this
Program can be loaded into absolute location in virtual memory space

35. Loading a Program Or set page table entries so they can be faulted in
Load from image file on disk into memory
1. Read header to determine segment sizes
2. Create virtual address space
3. Copy text and initialized data into memory
Or set page table entries so they can be faulted in
4. Set up arguments on stack
5. Initialize registers (including $sp, $fp, $gp)
6. Jump to startup routine
Copies arguments to $a0, … and calls main
When main returns, do exit syscall

36. Dynamic Linking Only link/load library procedure when it is called
Requires procedure code to be relocatable
Avoids image bloat caused by static linking of all (transitively) referenced libraries
Automatically picks up new library versions

37. Lazy Linkage Indirection table
Stub: Loads routine ID, Jump to linker/loader
Linker/loader code
Dynamically mapped code

38. Fallacies §2.18 Fallacies and Pitfalls
Powerful instruction  higher performance
Fewer instructions required
But complex instructions are hard to implement
May slow down all instructions, including simple ones
Compilers are good at making fast code from simple instructions
Use assembly code for high performance
But modern compilers are better at dealing with modern processors
More lines of code  more errors and less productivity
§2.18 Fallacies and Pitfalls

39. Fallacies Backward compatibility  instruction set doesn’t change
But they do accrete more instructions
x86 instruction set

40. Pitfalls Sequential words are not at sequential addresses
Increment by 4, not by 1!

41. Concluding Remarks Design principles Layers of software/hardware
1. Simplicity favors regularity
2. Smaller is faster
3. Make the common case fast
4. Good design demands good compromises
Layers of software/hardware
Compiler, assembler, hardware
MIPS: typical of RISC ISAs
c.f. x86
§2.19 Concluding Remarks

42. and, or, nor, andi, ori, sll, srl
Concluding Remarks
Measure MIPS instruction executions in benchmark programs
Consider making the common case fast
Consider compromises
Instruction class
MIPS examples
SPEC2006 Int
SPEC2006 FP
Arithmetic
add, sub, addi
16%
48%
Data transfer
lw, sw, lb, lbu, lh, lhu, sb, lui
35%
36%
Logical
and, or, nor, andi, ori, sll, srl
12% 4%
Cond. Branch
beq, bne, slt, slti, sltiu
34% 8%
Jump
j, jr, jal 2% 0%

43. Chapter 2 assignments
2.2.1, 2.3.1, 2.4.1, 2.4.4, 2.7.1, 2.7.2, , , , , , , , ,

44. Decoding Machine Language
Decode: 00AF8020hex
opcode: funct: shamt: 00000
rs: rt: rd: 10000
add $so, $a1, $t7

45. FIGURE 2.19 MIPS instruction encoding.
This notation gives the value of a field by row and by column. For example, the top portion of the figure shows load word in row number 4 (100two for bits 31−29 of the instruction) and column number 3 (011two for bits 28−26 of the instruction), so the corresponding value of the op field (bits 31−26) is two. Underscore means the field is used elsewhere. For example, R-format in row 0 and column 0 (op = two) is defined in the bottom part of the figure. Hence, subtract in row 4 and column 2 of the bottom section means that the funct field (bits 5−0) of the instruction is two and the op field (bits 31−26) is two. The floating point value in row 2, column 1 is defined in Figure 3.18 in Chapter 3. Bltz/gez is the opcode for four instructions found in Appendix B: bltz, bgez, bltzal, and bgezal. This chapter describes instructions given in full name using color, while Chapter 3 describes instructions given in mnemonics using color. Appendix B covers all instructions. Copyright © 2009 Elsevier, Inc. All rights reserved.