Presentation is loading. Please wait.

Presentation is loading. Please wait.

CIT 668: System Architecture

Similar presentations


Presentation on theme: "CIT 668: System Architecture"— Presentation transcript:

1 CIT 668: System Architecture
Computer Systems Architecture I

2 Topics System Components Processor Memory Storage Network
Operating System Images courtesy of Majd F. Sakr or from Wikipedia unless otherwise noted.

3 A Single CPU Computer Components

4 Von Neumann Architecture
Single storage for both data and commands Storage separate from control unit RAM CPU The Brain von Neumann

5 The 5 Von Neumann Components
Input/Output CPU and ALU Memory

6 Motherboard

7 The Processor

8 The Processor The Brain: a functional unit that interprets and carries out instructions (mathematical operations) Also called a CPU (actually includes CPU + ALU) Consists of hundreds of millions of transistors.

9 Instruction Set Architecture (ISA)
Every processor has its own set of operations Written in binary machine language (ML) Each instruction consists of operator + operand Assembly language is humanly-readable ML Category Example Arithmetic Add, subtract, multiply, divide Logic And, or, not, exclusive ov Program Control Branch (conditional), call, jump Data Movement Move, load, store I/O Read, write

10 Source Code to Machine Language

11 Program Execution Cycle
Fetch/Execute Cycle Fetch: retrieve instruction from memory Execute: decode instruction, fetch operands, execute instruction, store results to memory (if any) Fetch Decode Execute Store

12 Synchronous Execution
Each step waits for click tick to begin A 100 MHz processor uses a clock that ticks 100,000,000 times per second. Fetch Decode Execute Store Cycle speed of 1 GHz: billionths of a second

13 Processor Components

14 Processor Layout

15 From Sand to Silicon Wafers
Purification and heating to make a pure silicon crystal. Sand, made up of 25% silicon, is the starting point Slicing the crystal into 300mm wafers for use in photolitho- graphy. 100kg of % pure silicon crystal

16 Photolithography http://cnx.org/content/m1037/latest/

17 Packaging Wafer is cut into dies, each containing one processor.
Substrate, die, and heatspreader assembled to make final CPU product for use in a PC.

18 Processor Components: Control
Control Unit Processor’s supervisor Fetch/execute cycle Retrieve instruction Decode instruction Execute actions Program Counter (PC): stores address of instruction to be fetched. Instruction Register (IR): has instruction most recently fetched.

19 Processor Components: Datapath
Register File: General purpose storage locations inside processor that hold addresses or values. Arithmetic Logic Unit: Set of functional units that perform arithmetic and logic operations. A 32-bit processor has registers that are typically 32 bits in size.

20 Superscalar Architecture
Instead of one ALU, use multiple execution units Some execution units are identical to others Others are different: Integer, FPU, multi-media

21 AMD Athlon Architecture

22 Computer System Layers

23 Moore’s Law – Number of transistors doubles every 18 months
More transistors = Cheaper CPUs Higher speeds More features More cache Bring 1ns (11.8 in) cable to illustrate why shrinking transistors can improve speed

24 Improvements in CPU Clock Speed

25 Computation Produces Heat
LN2 cooling

26 Processor Power Density
Sun’s 10000 Surface Rocket Nozzle 1000 Nuclear Reactor 100 Power Density (W/cm2) Pentium IV Pentium III Pentium II 8086 10 Hot Plate Pentium Pro 4004 8008 8085 386 Pentium® 286 486 8080 Source: Intel 1 1970 1980 1990 2000 2010 Year

27 The Single CPU is History
What can you do with more transistors at same speed? Multicore CPUs Multiple processors (cores) on a single chip Run different programs on each core Some programs can be rewritten to run on multiple cores: PhotoShop, bzip2 Most of you are running multi-core 6-core opteron image from

28 2011 Server CPUs Intel Xeon AMD Opteron IBM Power 7 Sun Niagara 3
Up to to 3.3 GHz Up to 18 MB L3 cache AMD Opteron 4, 6, 8, or to 3.2 GHz Up to 12 MB L3 cache IBM Power 7 4, 6, or to 4.25 GHz 4 MB L3 cache per core (up to 32MB for 8-core) Sun Niagara 3 GHz 6 MB L2 cache

29 End of Moore’s Law Si ≈ 0.3 nm
Si ≈ 0.3 nm

30 Better Materials More Machines Better Algorithms
Where do we go from here? Better Materials GaAs Diamond More Machines Cloud Containers Better Algorithms Map Reduce Fuzzy Logic

31 Processor-Memory Gap


Download ppt "CIT 668: System Architecture"

Similar presentations


Ads by Google