1. ENG2410 Digital Design “Combinational Logic Design”
Fall 2017
S. Areibi
School of Engineering
University of Guelph

2. Resources Chapter #4, Mano Sections 4.1 Combinational Circuits
4.3 Decoding
4.4 Encoding
4.5 Multiplexers
4.6 Comb Function Implementations
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3. Week #4 Topics Decoders Encoders Multiplexers Demultiplexers
Combinational circuit Implementation
Encoders
Priority Encoders
Multiplexers
Combinational Circuit Implementation
Demultiplexers
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4. Devices on a Bus Enable Device #0 Control Unit Disable Device #1
I have 4 devices to put info on a Bus
I must have only one device active at a time!
I will need 4 wires from my Control Unit
If I need to communicate with more devices then I will need many wires!!
Control
Unit
Enable
Device #0
Disable
Device #1
Disable
Device #2
Disable
Device #3
BUS

5. Address Decoding Device #0 Control Unit Device #1 Device #2 Device #3
I have 4 devices to put info on a Bus
I must have only one device active at a time!
But! I can afford to have only 2 wires from my control unit
Control
Unit
Device #0 1
Device #1
Device #2
Device #3
BUS

6. Decoders Are circuits with n inputs and 2n outputs
Drives high the output corresponding to binary code of input
Several Applications: Address Decoding, … D0 A D1

7. 2-to-4 Line Decoder
Notice they are minterms

8. Other Decoders Examples: 3-to-8 Decoder 4-to-16 Decoder 3-to-8 Line
Binary to Octal,
Binary to Hex, e.t.c
3-to-8
Line
Decoder
4-to-16
Line
Decoder 3 8 4 16

9. Truth Table, 3-to-8 Decoder
Example: Binary to Octal, Binary to Hex, e.t.c
Notice they are minterms

10. 3-to-8 Line Decoder Schematic

11. 2-to-4 with Enable
Why use an Enable?

12. Enable Used for Expansion1 1 1 1 1 1 1 1 1 1 1 1 1

13. Usage for Decoders Binary to Octal/Hex converters.
Selecting memory banks, for example 4 memory banks can be selected individually using 2 address lines.
Implementing logic circuits!
Decoders are used in Micro Computer Interfacing for Keyboard and Display applications.

14. 1. Address Decoding Memory Bank #1 CPU Memory Bank #2 Memory Bank #3

15. 2. Decoders as General-purpose Logic
n:2n decoder implements any function of n variables
With the variables used as control inputs
Enable inputs tied to 1 and
Appropriate minterms summed to form the function
Decoder generates appropriate
minterm based on control signals
(it "decodes" control signals)
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16. Decoders as General-purpose Logic
Example: Implement the following Boolean functions
S(A2,A1,A0) = SUM(m(1,2,4,7))
C(A2,A1,A0) = SUM(m(3,5,6,7))
Since there are three inputs, we need a 3-to-8 line decoder.
The decoder generates the eight minterms for inputs A0,A1,A2
An OR GATE forms the logical sum minterms required.
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17. Decoders as General-purpose Logic
S(A2,A1,A0) = SUM(m(1,2,4,7)) S
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18. Decoders as General-purpose Logic
C(A2,A1,A0) = SUM(m(3,5,6,7)) C
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19. Example F1 = A' B C' D + A' B' C D + A B C D A B
0 A'B'C'D' 1 A'B'C'D 2 A'B'CD' 3 A'B'CD 4 A'BC'D' 5 A'BC'D 6 A'BCD' 7 A'BCD 8 AB'C'D' 9 AB'C'D 10 AB'CD' 11 AB'CD 12 ABC'D' 13 ABC'D 14 ABCD' 15 ABCD
4:16 DEC
Enable C D F1
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20. Encoder Encoder is the opposite of decoder Examples:
2n inputs (or less – maybe BCD in)
n outputs
Examples:
Octal to binary conversion
Hexadecimal to binary conversion

21. Octal to Binary Encoder

22. Design of Encoder
A0 = D1 + D3 + D5 + D7

23. Multiplexer (or Mux)
Selects one of a set of inputs to pass on to output
For Every 2n inputs we need n select lines
Applications: Useful for choosing from sets of data
Memory or register to ALU
In0
Out
In1
MUX
In2
In3 S0 S1

24. 2-Input Multiplexer

25. 4-to-1 Line Multiplexer

26. Quad 2-to-4 Line Mux
Select one set of 4 lines

27. Implementing Logic
2n:1 multiplexer implements any function of n variables
With the variables used as control inputs and
Data inputs tied to 0 or 1
In essence, a lookup table
Example: F(A,B) = m0 + m = A'B' + AB’ A B F 1

28. Muxes as General-purpose Logic
2n:1 multiplexer implements any function of n variables
With the variables used as control inputs and
Data inputs tied to 0 or 1
In essence, a lookup table
Example: F(A,B,C) = m0 + m2 + m6 + m = A'B'C' + A'BC' + ABC' + ABC A B C F 1 S2
8:1 MUX S1 S0 F A B C
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29. Muxes as General-purpose Logic
2n-1:1 mux can implement any function of n variables
With n-1 variables used as control inputs and
Data inputs tied to the last variable or its complement
Example:
F(A,B,C) = m0 + m2 + m6 + m = A'B'C' + A'BC' + ABC' + ABC
Not Optimized
Optimized C A B S2
8:1 MUX S1 S0
A B C F
C' C' A B S1 S0 F
4:1 MUX
C' C' 0 1 F
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30. Demultiplexer
Takes one input out to one of 2n possible outputs

31. VHDL

32. Decoder: (VHDL  Data Flow)
Example: 2-to-4 decoder D3
entity dec_2_to_4 is
port (
A0, A1: in std_logic;
D0, D1, D2, D3: out std_logic);
end entity dec_2_to_4;
A(1) D2
Interface
A(0) D1 D0
architecture dataflow1 of dec_2_to_4 is
Signal A0_n, A1_n: std_logic;
begin
A0_n <= not A0;
A1_n <= not A1;
D0 <= A0_n and A1_n;
D1 <= A0 and A1_n;
D2 <= A0_n and A1;
D3 <= A0 and A1;
end architecture dataflow1;
A0_n
A1_n
Functionality
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33. When Else Statement mux: Y <= D0 when S1 = ‘0’ and S0 = ‘0’ else

34. Decoder: Data Flow #2 Interface Functionality Example: 2-to-4 decoder
entity dec_2_to_4 is
port (
A : in std_logic_vector(1 downto 0);
D : out std_logic_vector(3 downto 0) );
end entity dec_2_to_4;
architecture dataflow2 of dec_2_to_4 is
begin
D <= "0001" when A = "00" else
"0010" when A = "01" else
"0100" when A = "10" else
"1000" when A = "11" else
"XXXX";
end architecture dataflow2;
A(1)
D(2)
Interface
A(0)
D(1)
D(0)
A(1..0)
D(3..0) 1
Functionality
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35. Dataflow VHDL Description of 4-to-1 Multiplexer
-- 4-to-1 Line Mux; Conditional Dataflow VHDL Descrip
library ieee;
use ieee.std_logic_1164.all
entity multiplexer_4_to_1 is
port (S: in std_logic_vector(1 downto 0);
I: in std_logic_vector(3 downto 0);
Y: out std_logic;
end multiplexer_4_to_1;

36. Cont .. Dataflow VHDL Description
architecture function_table of multiplexer_4_to_1 is
-- Using When Else
Begin
Y <= I(0) when S = “00” else
I(1) when S = “01” else
I(2) when S = “10” else
I(3) when S = “11” else
`X’;
end function_table;

37. VHDL Design Styles VHDL Design Styles dataflow behavioral
(algorithmic)
structural
Concurrent
statements
Components and
interconnects
Sequential statements
Registers
State machines
Test benches
Subset most suitable for synthesis

38. Structural VHDL Description of 2-to-4 Line Decoder

39. Structural VHDL Description “Entity Declaration”
-- 2-to-4 Line Decoder; structural VHDL Description
library ieee;
use ieee.std_logic_1164.all
entity decoder_2_4_w_enable is
port (EN, A0, A1 : in std_logic;
D0, D1, D2, D3 : out std_logic);
end decoder_2_to_4_w_enable;

40. Structural VHDL Description (Signals)
A1_n
A0_n N0 N1 N2 N3

41. Structural VHDL Description (Components)
architecture structural1_1 of decoder_2_to_4_w_enable is
component NOT1
port(in1: in std_logic;
out1: out std_logic);
end component;
component AND2
port(in1, in2: in std_logic;

42. Structural VHDL Description (Connecting components)
A1_n
A0_n
architecture structural1_1 of decoder_2_to_4_w_enable is
-- component NOT1 declaration
-- component NAND2 declaration
signal A0_n, A1_n, N0, N1, N2, N3: std_logic;
begin
g0: NOT1 port map (in1 => A0, out1 => A0_n);
g1: NOT1 port map (in1 => A1, out1 => A1_n); ……
end structural_1;
component NOT1
port(in1: in std_logic;
out1: out std_logic);
end component;

43. Structural VHDL Description (Connecting components)
architecture structural1_1 of decoder_2_to_4_w_enable is
-- component NOT1 declaration
-- component NAND2 declaration
signal A0_n, A1_n, N0, N1, N2, N3: std_logic;
begin
g0: NOT1 port map (in1 => A0, out1 => A0_n);
g1: NOT1 port map (in1 => A1, out1 => A1_n);
g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0);
g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1);
g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2);
g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3);
g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0);
g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1);
g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2);
g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3);
end structural_1;

44. 2-to-4 Line Decoder: Complete Design
-- 2-to-4 Line Decoder; structural VHDL Description
library ieee;
use ieee.std_logic_1164.all
entity decoder_2_4_w_enable is
port (EN, A0, A1 : in std_logic;
D0, D1, D2, D3 : out std_logic);
end decoder_2_to_4_w_enable;
A1_n
A0_n
architecture structural1_1 of decoder_2_to_4_w_enable is
-- component NOT1 declaration
-- component NAND2
signal A0_n, A1_n, N0, N1, N2, N3: std_logic;
begin
g0: NOT1 port map (in1 => A0, out1 => A0_n);
g1: NOT1 port map (in1 => A1, out1 => A1_n);
g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0);
g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1);
g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2);
g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3);
g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0);
g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1);
g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2);
g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3);
end structural_1;

45. End Slides

46. Revisiting Encoder!! Why?
Only ONE input is allowed to be active at a time!

47. What’s the Problem? What if D3 and D6 both high?
Simple OR circuit will set A to 111
This is an issue!!!!
Solution?

48. Priority Encoder Chooses one with highest priority
Largest number, usually
“X” in input == 0 or 1
compact Truth Table

49. Unfolding the Compact Truth Table
What if all inputs are zero?

50. Need Another Output!
A Valid Output!

51. Expanded Truth Table (A0)X 1
D1D0
D3D2 00 01 11 10 x 1 00 01 11 10
A0 = D3 + D2D1

52. Valid is OR of all inputs

53. Structural VHDL Description of 4-to-1 Line Multiplexer
S_n(0:1)
D(0:3)
N(0:3)

54. Cont .. Structural VHDL Description of 4-to-1 Multiplexer
-- 4-to-1 Line Multiplexer; structural VHDL Description
library ieee;
use ieee.std_logic_1164.all
entity multiplexer_4_to_1_st is
port (S: in std_logic_vector(0 to 1);
I: in std_logic_vector(0 to 3);
Y: out std_logic;
end multiplexer_4_to_1_st;

55. Cont .. Structural VHDL Description of 4-to-1 Multiplexer
architecture structural_2 of multiplexer_4_to_1_st is
component NOT1
port(in1: in std_logic;
out1: out std_logic);
end component;
component AND2
port(in1, in2: in std_logic;
component OR4
port(in1, in2, in3, in4: in std_logic;

56. Cont .. Structural VHDL Description of 4-to-1 Multiplexer
architecture structural_2 of multiplexer_4_to_1_st is
-- component NOT1 AND2 OR4 declarations
signal S_n : std_logic(0 to 1);
signal D, N : std_logic_vector(0 to 3);
begin
g0: NOT1 port map (S(0), S_n(0));
g1: NOT1 port map (S(1), S_n(1));
g2: AND2 port map (S_n(1), S_n(0), D(0));
g3: AND2 port map (S_n(1),S(0), D(1));
g4: AND2 port map (S(1),S(0), D(3));
g5: AND2 port map (S(1), S(0), D(3));
g6: AND2 port map (D(0), I(0), N(0));
g7: AND2 port map (D(1),I(1), N(1));
g8: AND2 port map (D(2),I(2),N(2));
g9: AND2 port map (D(3),I(3), N(3));
g10: OR4 port map (N(0), N(1), N(2), N(3), Y);
end structural_2;