1. Part II A workshop by Dr. Junaid Ahmed Zubairi
VLSI DESIGN USING VHDL
Part II
A workshop by
Dr. Junaid Ahmed Zubairi

2. Workshop References VHDL by Amos Zaslavsky (http://www.pet.ac.il )
Fundamentals of Digital Design by Brown and Vranesic, McGraw Hill
Altera Training Modules

3. Outline Some Example Designs Generate Statements Example Project
Shift Operations

4. Some Example Designs
A multiplexer is a circuit that has several inputs and only one output line
One of the inputs is selected using selection lines for onward connection with the output
In VHDL, multiplexers can be achieved using conditional assignment statements

5. A 4-to-1 Multiplexer library ieee; use ieee.std_logic_1164.all;
entity mux4to1 is
port (Sel:in std_logic_vector(0 to 1);
A:in std_logic_vector(0 to 3); Y:out std_logic);
end mux4to1;
architecture mux1 of mux4to1 is
begin
Y <= A(0) when Sel = ’00’ else
A(1) when Sel = ’01’ else
A(2) when Sel = ’10’ else
A(3) when others;
end mux1;

6. An 8-Bit Register With Asynchronous Reset
library ieee;
use ieee.std_logic_1164.all;
entity reg8 is
port (D:in std_logic_vector(7 downto 0);
reset,clk:in std_logic; Q:out std_logic_vector(7 downto 0));
end reg8;
architecture myreg of reg8 is
begin
process(reset,clk)
if reset= '0' then Q<= " ";
elsif clk'event and clk='1' then Q<=D;
end if;
end process;
end myreg;

7. Generate Statements
You can generate several components using for..generate statements in VHDL
For example, derive a 16-to-1 Multiplexer from the given 4-to-1 Multiplexer
The source code is given

8. Generate Statements library ieee; use ieee.std_logic_1164.all;
entity mux16to1 is
port (Sel:in std_logic_vector(0 to 3);
A:in std_logic_vector(0 to 15); Y:out std_logic);
end mux16to1;
architecture mux2 of mux16to1 is
Begin
Signal m:std_logic_vector(0 to 3);
Component mux4to1 is
Port (Sel:in std_logic_vector(0 to 1);
A:in std_logic_vector(0 to 3); Y:out std_logic);
end component;

9. Generate Statement Begin G1: for I in 0 to 3 generate
Muxes: mux4to1 port map (Sel(0 to 1), A(4*i to 4*i+3), m(i));
End generate;
Mux5: mux4to1 port map (Sel(2 to 3), m(0 to 3), Y);
End structure;

10. Example Design Project
Using the 4-bit comparator designed earlier, develop a circuit that contains a comparator and a 4-bit register. The register will be loaded with a 4-bit number with the rising edge of the clock. Another four bit number will be applied directly to the other input of the comparator. Show the results

11. Shift Operations
Do not use built in shift operations. It is preferable to slice and catenate
For example Reg(15 downto 0) can be shifted as:
Reg(14 downto 0) & Reg(15)

12. 3 Types of Circuits

13. Switch~Case VHDL Style
Expression 1 when bool-cond1 else
Expression 2 when bool-cond2 else
Expression 3 when bool-cond3 else
Default-expression;

14. Inferred Logic

15. Another Style With Expression select A <= Expression1 when value0;
Expression2 when value1 to value2;
Expression3 when value3|value4;
Expression4 when others;

16. Inferred Logic

17. Assignment Types

18. Process Rules Conditional and selected assignments are NOT allowed
You may use case, if statements and nested if’s
Do not use Wait statements
Use only static for loops

19. Be Careful

20. Sensitivity List Include all RHS side signals of assignment statements
Include all signals in conditions (if and case)
Otherwise you produce sick hardware with wrong feedback paths
Do not include EXTRA redundant inputs to the list

21. Unintended Latches

22. Results

23. How to avoid Parasites Assign a value to all outputs in ALL cases
There is a long way to do it and a short way to do it

24. Long Way

25. Short Way

27. Warning
In Data flow architecture, multiple assignments result in contention
Begin with default assignments when writing code for case statements