1. Designing electronics for a TOF Forward PID for SuperB D. Breton & J
Designing electronics for a TOF Forward PID for SuperB D.Breton & J.Maalmi (LAL Orsay), E.Delagnes (CEA/IRFU)

2. Introduction
In the view of the TOF FPID solution for SuperB, we have installed a test setup at SLAC in order to estimate our ability to measure the time of flight of muons between two quartz bars with a sufficient precision.
To this end, we have developped dedicated electronics on the base of a synchronous sixteen channel acquisition system based on 8 two-channel WaveCatcher V5 boards.
Technical challenge: keeping the board’s 10ps time precision at the crate level
The system works with a common synchronous clock
There we take benefit of the external clock input of the WaveCatcher
It is self-triggered but synchronized with the rest of the CRT
Rate of cosmics is low thus computer time tagging of events is adequate (if all computers are finely synchronized)
Like the WaveCatcher, data acquisition is based on 480Mbits/s USB. .
The two-bar setup is rather simple, but the capacity for electronics to measure all channels simultaneously with a 10ps time precision is not.
=> we will describe the state of the art for high precision time measurement
=> we will explain here why we think analog memories are the right solution for this type of measurement
=> we will describe the WaveCatcher module
=> we will present the current 16-channel setup and how we intend to move toward prototyping a 672-channel system

3. The USB Wave Catcher board V5
Reference clock: 200MHz => 3.2GS/s
Pulsers for reflectometry applications
1.5 GHz BW
amplifier.
Board has to be USB powered
=> power consumption < 2.5W
480Mbits/s USB interface
µ USB
Trigger
input
2 analog
inputs. DC
Coupled.
Clock
input
Trigger
output
+5V
Jack
plug
Trigger
discriminators
SAM Chip
Dual 12-bit ADC
Cyclone FPGA

4. Clock and control board
Electronics setup
USB hub
From
QTZ3 8
16 amplifiers
Patch panel
36dB
Amp
Trig out
CH0
CH1
Clk in
Trig in
Trig out
CH0
CH1
Clk in
Trig in
Trig out
CH0
CH1
Clk in
Trig in
Trig out
CH0
CH1
Clk in
Trig in
Trig out
CH0
CH1
Clk in
Trig in
Trig out
CH0
CH1
Clk in
Trig in
Trig out
CH0
CH1
Clk in
Trig in
Trig out
CH0
CH1
Clk in
Trig in
USB
36dB
Amp
Ext trig out
Ext trig in
USB
USB
USB
USB
USB
USB
USB
USB
Clk out 8
Trig out 8
Trig in 8
36dB
Amp
36dB
Amp
8 USB WaveCatcher V5
Clock and control board
DAQ PC

5. Clock and control board (1)
From WaveCatchers
To WaveCatchers
From QTZ3
CRT mode : when the controller board detects a coincidence between an external trigger from QTZ3 and one of the sixteen channels, it sends through USB a specific interrupt to the PC in order to start the data readout.

6. Clock and control board (2)
USB interface
=> 480Mbits/s
Zero jitter clock buffer
Clock outputs
Trig outputs
µ USB
Trigger
Input (NIM)
Trigger
Output (NIM)
+5V
Jack
plug
Pulse
output
Trig inputs
Reference clock: 200MHz
Cyclone FPGA

7. Full crate

8. Back of the crate

9. Time performance of multi-board system
Mean differential jitter is of about 12ps rms which corresponds to 8.5 ps rms of time precision per pulse

10. Two-bar setup at SLAC

11. The whole system

12. For the experiment current results, see Leonid’s talk …
One cosmic event
Recycled 6U crate
Naked WaveCatchers
mounted on 3U carrier boards
For the experiment current results, see Leonid’s talk …

13. Comments about SLAC setup
Baseline uses sixteen individual 36 dB amplifiers but a solution with a board housing 16 amplifiers with programmable gain is under study
Indeed, the maximum gain possible on the WaveCatcher board while keeping a reasonable bandwidth (300 MHz) is of the order of 15 (23 dB)
This is not sufficient for the MCPPMT so since an external amplifier is requested, let’s let him do the job !
Sampling depth of only 256 cells made it a litle bit difficult to stop the sampling in the memories soon enough:
A longer sampling depth would be more convenient
If long enough (>200ns), it would permit a true coincidence with the CRT trigger
Driving 9 USB peripherals is tricky (>7) so it would be nice to concentrate event data before feeding USB
=> more channels on a board

14. Towards a high scale system …

15. The new SAMLONG ASIC
SAM was a great demonstrator for precision time measurement.
But in parallel there was a need for longer depth analog memories
A chip like SAM with 1024 cells and compatible with the WaveCatcher board was designed: SAMLONG. This chip also includes:
a ramp TDC (“vernier”) for tagging the trigger arrival time (like in our former MATACQ chip).
New input buffers (slew rate, power)
New readout amplifiers (noise)
Output multiplexor (single ADC)
Internal programmable posttrig
Target: same performances as SAM but with less power (300mW => 200mW / 2ch)
Everything we learnt from SAM for time precision was taken into account
SAMLONG was submitted in April 2010 and received in September
It was mounted on a WaveCatcher V4 and worked immediatly !
It is a fruitful source of informations for the future design of a new chip optimized for time measurement …

16. SAMLONG vs SAM
SAM better than SAMLONG after correction, but SAMLONG better than SAM
before correction despite the factor 4 in length
=> improvement in the design of SAMLONG but it is less easy to calibrate finely

17. From a crate to a 16-channel board
8 x 75 = 600 mm !
145 mm

18. Under design: a 16-channel WaveCatcher
SAMLONG Chip 1024 pts GS/s 2 Channels
Dual 12 bits
ADC
4 Analog Input
Trigger In/out
FPGA
VME Format
USB 480 Mbits/s
Optical fiber output
Based on the very encouraging results of the 16-channel crate, we started the design of a 16-channel WaveCatcher board
This board will be compatible with both SAM (256 cells/ch) and SAMLONG (1024 cells/ch)
The board can be synchronized externally => possibility to scale the system up to 320 channels in a crate
The first prototype will be available in September 2011

19. Board features (not exhaustive)
Possibility to add a individual DC offset on each signal
Possibility to chain channels by groups of 2
2 individual trigger thresholds on each channel
External and internal trigger + numerous modes of triggering on coïncidence (11 possibilities including two pulses on the same channel => useful for afterpulse studies
Embedded digital CFD for time measurement
Embedded signal amplitude extraction
Embedded charge mode (integration starts on threshold or at a fixed location) => high rates (~ 3.5 kEvents/s)
2 extra memory channels for digital signals
One pulse generator on each input
External clock input for multi-board applications
Embedded USB and Ethernet interfaces

20. Extracting the time from the signal: CFD
The easiest way to extract the time information from a digitized signal is to perform a digital Constant Fraction Discrimination (CFD)
Indeed, a simple threshold method introduces Time Walk which depends on the signal amplitude
in order to remove the time walk, threshold has to be set as a constant fraction of the signal amplitude
Algorithm can be as simple as looking for the closest sample to the peak and performing a linear interpolation between samples around the threshold => easy to implement within a FPGA, then into an ASIC if necessary.
More complex algorithms based on multi-sample digital filtering may improve the resolution A1
Δt ~ 0
relative threshold :
constant fraction
of the peak! A2 A3
k x A1
k x A2
k x A3 V t
Fixed threshold t V
Δt : time walk

21. Board Schematic Principle
SAMLONG: 3.2GS/s samples ~ 320ns => Trigger has to come back within 250 ns C O N T R L E B A D
Ch0 +
Optional:
if more than
16 channels
Low Threshold - +
High Threshold -
Ch1 +
Low Threshold
½ Front End
FPGA
(TimeStamp,Q,A)
L1 Trigger -
FPGA
Controller +
High Threshold -
L1 primitives
Run, read
Event data
Ch0
SAMLONG
clk
Ch1
12-bit
ADC
x 8
USB
USB

22. Status of
PCB design
(as of last Friday)

23. Towards a ps TDC …
In order to build a real TDC targetting the ps level, adding an analog memory to a usual DLL TDC permits relieving the walk constraint on the discriminator and improving the time precision by an order of magnitude
Here the Delay Line is servo-controlled and can be as short as the signal to measure => very good time resolution can be envisaged
Amplitude and charge can also be extracted from waveform.
Critical path
for time
measurement

24. Targetting the final design of SuperB TOF
Final design will permit readout of 672 channels.
We need hit charge and time
Readout window ~ 5ns => 15 samples per hit read at ~ 20 MHz => total memory readout time of ~750 ns per hit
Mean pixel hit rate ~ 500 kHz reduced by >90% by sector photon counting (>5)
Analog memory will have to avoid creating dead-time => integrated derandomizer design is under study
Block diagram of one channel
MCPPMT
Level1 trigger
Amplifier
Auto-triggered
analog memory
2-5 GS/s
ADC
CFD +
latency buffer
(PRO ASIC 3
Actel FPGA)
Control
To DAQ
On-detector
Off-detector (1 to 2 meters away)

25. Conclusion
The USB WaveCatcher 16-channel crate has proven that the use of matrix analog memories in the field of ps time measurement was an effective solution.
Lab timing measurements showed a stable single pulse resolution < 10 ps rms
CRT measurements at SLAC confirmed these performances
Even the simplest CFD algorithm can give a good timing resolution (10% loss)
We started the design of a 16-channel version of the board
We were able to squeeze the design to fit on a single board
This will permit testing the extension of time precision to >100 channels
We will soon design a chip fully optimized for time measurement
We think it is possible to reach 5ps precision with the current 0.35µm technology
Even less with the new 0.18µm
We will study a version with an integrated derandomizer in order to drastically reduce the dead-time
Then we should be fully ready for the final design for SuperB …