1. Design of AND and NAND Logic Gate Using
IEEE Asia Pacific Conference on Circuits and Systems, Singapore Dec. 4-7, 2006, pp
Design of AND and NAND Logic Gate Using
NDR-Based Circuit Suitable for CMOS Process
Kun Shan University
Department of Electronic Engineering
Dong-Shong Liang, Kwang-Jow Gan, Cher-Shiung Tsai,
and Yaw-Hwang Chen
Abstract
AND and NAND logic gate based on the negative differential resistance (NDR) device is demonstrated. This NDR device is made of metal-oxide-semiconductor field-effect-transistor (MOS) devices that could exhibit the NDR characteristic in the current-voltage curve by suitably arranging the MOS parameters. The devices and circuits are implemented by the standard 0.35μm CMOS process.
Fig. 5 The load-line analysis for the (a) monostable case (VS<2VP), (b) bistable case.
Fig. 7 The load-line analysis for the
NAND gate.
Fig. 6 The load-line analysis for the
AND gate.
Fig. 1 The circuit configuration for a MOS-NDR device.
Fig. 8 The peak current of the NDR
I-V curvecan be controlled by the
magnitude of T1 voltage
Fig. 9 The measured result for
the AND gate operation.
Fig. 2 The Hspice simulated I-V characteristic for a
MOS-NDR device by modulating the
Vgg values from 1.5V to 3.3V.
Fig. 10 The measured result for the NAND gate operation.
Conclusion
We have shown the two-peak I-V characteristics with two MOS-HBT-NDR devices connected in parallel. Using the two-peak I-V characteristics with another MOS-HBT-NDR device as a load, a five-valued logic circuit is demonstrated and simulated by the standard 0.35μm SiGe BiCMOS process. Because all of the devices used in this circuit are fully composed of MOS devices, this MOS-HBT-NDR logic circuit will be convenient to integrate with other Si-based or SiGe-based devices and circuits to achieve the system-on-a-chip.
Fig. 3 The peak current of MOS-NDR device
could be controlled by the VG voltage.
Fig. 4 The circuit configuration of the logic circuit.