1. VHDL Basics

2. VHDL kod yerleşimi kütüphaneler Dış görünüş (entity: varlık)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity and_gate_3_1 is port ( a:in std_logic; b:in std_logic; c:in std_logic; d:out std_logic); end and_gate_3_1; architecture behaviour of and_gate_3_1 is begin d<=a and b and c; end behaviour;
kütüphaneler
Dış görünüş (entity: varlık)
İşleyişi, yapısı
(architecture: mimari)

3. entity NAME_OF_ENTITY is port (signal_names: mode type;
  Entity Declaration
The entity declaration defines the NAME of the entity and lists the input and output ports. The general form is as follows,
entity NAME_OF_ENTITY is
port (signal_names: mode type;
signal_names: mode type; :
signal_names: mode type);
end [NAME_OF_ENTITY] ;

4. Modes & Types
  mode: is one of the reserved words to indicate the signal direction:
  in – indicates that the signal is an input
out – indicates that the signal is an output of the entity whose value can only be read by other entities that use it.
  inout – the signal can be an input or an output.
        type: a built-in or user-defined signal type.
o       bit – can have the value 0 and 1
o       bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7)
o       std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: o       boolean – can have the value TRUE and FALSE
o       integer – can have a range of integer values
o       real – can have a range of real values
o       character – any printing character
o       time – to indicate time

5. port ( a, b : in std_logic; sum, carry :out std_logic);
  Entity Declaration
entity half_adder is
port ( a, b : in std_logic;
sum, carry :out std_logic);
end half_adder; b a
sum
carry
The interface is a collection of ports
Ports are a new programming object: signal
Ports have a type: std_logic
Ports have a mode: in, out, inout (bidirectional)

6. Architecture body architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations:
begin
-- Statements:
end architecture_name;

7. Architecture body architecture behavior of half_adder is begin
entity half_adder is
port (a, b : in std_logic;
sum, carry :out std_logic);
end half_adder;
architecture behavior of half_adder is
begin
sum <= a xor b;
carry <= a and b;
end behavior; b a
sum
carry
Description of events on output signals in terms of events on input signals: the signal assignment statement

8. VHDL Operators
Logical Operators not, and, nand, or, nor, xor, xnor - works on types BIT, BIT_VECTOR, BOOLEAN - vectors must be same length - the result is always the same type as the input
Numerical Operators "addition" "subtraction" * "multiplication" / "division" mod "modulus« rem "remainder" abs "absolute value" ** "exponential"
- works on types INTEGER, REAL - the types of the input operands must be the same
"The result of the rem operator has the sign of its first operand while the result of the mod operators has the sign of the second operand." Taken from 

9. VHDL Operators
Relational Operators Output is always BOOLEAN (TRUE, FALSE) - works on types: BOOLEAN, BIT, BIT_VECTOR, CHARACTER, INTEGER, REAL, TIME, STRING = "equal« /= "not equal" < "less than« <= "less than or equal" > "greater than« >= "greater than or equal«
Shift Operators works on one-dimensional arrays - works on arrays that contain types BIT, BOOLEAN sll "shift left logical« srl "shift right logical" sla "shift left arithmetic« sra "shift right arithmetic" rol "rotate left« ror "rotate right«
Concatenation Operator
- combines objects of same type into an array
& "concatenate" ex) New_Bus <= ( Bus1(7:4) & Bus2(3:0) )

10. signals Internal signals connect components behavior sig1
ENTITY fewgates IS
PORT (
A : IN STD_LOGIC;
B : IN STD_LOGIC;
C : IN STD_LOGIC;
Y : OUT STD_LOGIC );
END fewgates;
behavior
sig1
ARCHITECTURE c1_behavior OF fewgates IS
SIGNAL sig1: STD_LOGIC;
BEGIN
sig1 <= (NOT A) AND (NOT B);
Y <= C OR sig1;
END c1_behavior;
Internal signals connect components

11. component Half adder alt modül yapılarak full adderda kullanılacaktır.
Half adder «ha»
full adder «fa»

12. component
Alt modüllerin sağ taraflarında kalan boşluklara virgülden önceye bağlanacak port ismi yazılarak. bağlantılar yapılır.
Yazılacak başka kod varsa (örnekte ‘or’ işlemi) kodun devamına yazılır.

13. component

14. process process (sensitivity_list) declarations; begin
sequential statement;
. . .
end process;
Contains a set of sequential statements to be executed sequentially
The whole process is a concurrent statement
Can be interpreted as a circuit part enclosed inside of a black box

15. process Process with sensitivity list.
Interpretation: “black box, indivisible circuit part”.
Sensitivity list
The execution of the process is initiated whenever an event occurs on any of the signals in the sensitivity list

16. syntax for IF, CASE, WITH and WHEN
!!! Inner of process !!!

17. syntax for IF, CASE, WITH and WHEN
!!! Inner of process !!!

18. syntax for IF, CASE, WITH and WHEN
!!! Out of process !!!

19. syntax for IF, CASE, WITH and WHEN
!!! Out of process !!!