1. Need for high performance Data Plane
Sujata Tibrewala
Networking Developer Evangelist
software.intel.com/networking

3. software.intel.com/networking
Network Functions
software.intel.com/networking

4. Networking Software Components.
software.intel.com/networking

5. software.intel.com/networking
NFV Model
Current Model
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6. Need for efficient Data Plane
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7. software.intel.com/networking
Packet processing
Packet sanity -> CRC calculation
VLAN tag present ? -> TPID
Ingress/Egress VLAN Filtering -> MAC + Port+ VLAN membership
SRC learning -> MAC + PORT
DEST MAC Learning -> MAC + port
QOS -> PCP
software.intel.com/networking

8. software.intel.com/networking
Packets per second
Frame Part
Minimum Frame Size
Maximum Frame Size
Inter Frame Gap (9.6 ms)
12 bytes
MAC Preamble (+ SFD)
8 bytes
MAC Destination Address
6 bytes
MAC Source Address
MAC Type (or length)
2 bytes
Payload (Network PDU)
46 bytes
1,500 bytes
Check Sequence (CRC)
4 bytes
Total Frame Physical Size
84 bytes
1, 538 bytes
Table 1. Maximum Frame Rate and Throughput Calculations For a 1-Gb/s Ethernet Link
[1,000,000,000 b/s / (84 B * 8 b/B)] == 1,488,096 f/s (maximum rate)
software.intel.com/networking

9. Packet rate/Cycle calculations
40gbps -> 80 mpps Or
One packet every 12.5 ns -> pipeline cycle time
If SRAM has 2 ns cycle time
More than 6 memory look ups cannot be done
software.intel.com/networking

10. Packet processing explosion VxLAN
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11. Traffic Management/scheduling
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12. Traffic Management/scheduling
software.intel.com/networking

13. Traffic Management/scheduling
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14. Traffic Management/scheduling
software.intel.com/networking

15. Complexity of Packet processing?
So how do we solve this problem?

16. Network Architecture for Enterprise & Private Clouds -Gautum Kulkarni, Zero Stack DPDK Perf. Optimizations with OVS-DPDK -M Jay , Intel Open vSwitch with DPDK for Inter-VM - Ashok Emani

17. Packet processing explosion GRE
software.intel.com/networking