1. COMPUTER ARCHITECTURE
Er. Anupa Dhungel
Cell:

2. Unit 3 – Fundamentals of Computer Organization and Design
Computer Register
Computer Instructions
Instruction Cycle
Input and Output and Interrupt
Basic Computer Design and Accumulator Logic

3. Basic Concept Computer Architecture:
It is those attributes of a system that have a direct impact on the logical execution of a program.
It is concerned with the structure and behavior of the computer as seen by the user.
It includes:
The instruction set.
The number of bits used to represent various data types.
I/O mechanisms.
Memory addressing techniques.

4. Basic Concept Computer Organization:
It refers to the operational units and their interconnections that realize the architectural specifications.
It is concerned with the way the hardware components operate and the way they are connected together to form the computer system.
Examples are things that are transparent to the programmer:
control signals.
interfaces between computer and peripherals.
the memory technology being used.

5. Description of basic computer
Computers are the digital devices that performs the various computational task.
Digital means there is the process of representing the information by the help of the certain discrete values.
Information is represented in digital computers in terms of bits.
By various coding techniques these groups of bits can not only represent numbers but also other discrete symbols.

6. Description of basic computer
A computer system is sub-divided into two functional entities: hardware and software.
Hardware consists of all electronics components.
Software consists of instruction and data that the computer manipulate to perform various tasks.

7. Description of basic computer

8. Description of basic computer
Application software is all the computer software that causes a computer to perform useful tasks beyond the running of the computer itself.
System software is computer software designed to operate and control the computer hardware and to provide a platform for running application software.
Computer hardware is the collection of physical elements that comprise a computer system

9. Description of Basic Computer

10. Description of Basic Computer
Hardware consist of three major parts:
The central processing unit(CPU):
It has ALU for manipulating the data, registers for storing data and instructions, and control circuits for fetching and executing instructions.
Memory:
Memory of a computer contains storage for instructions and data.
The input-output processor
It contains electronic circuits for communicating and controlling the transfer of information between the computer and input or output devices or user.

11. Memory Hierarchy

12. Basic Concept
Each processor has large number of registers, buses, micro-operations, machine instructions, etc.
Basic computer has processor and memory.
The memory has 4096 words in it
4096 = 212, so it takes 12 bits to select a word in memory
Each word is 16 bits long.
The instructions of a program, along with any needed data are stored in memory.
The CPU reads the next instruction from memory. It is placed in an Instruction Register (IR).

13. Instruction Code Operation Code:
The operation code of an instruction is a group of bits that define such operations as add, subtract, multiply, shift, and complement.
Micro-operation:
Micro-operation is the elementary operation performed with the data stored in the registers.
Types of Micro-Operation:
a)Register transfer.
b)Arithmetic transfer.
c)Logic.
d)Shift.

14. Instruction Code
It is a group of used to perform a particular operation on the data stored in computer.
Processor fetches an instruction from memory and decodes the bits to execute the instruction.
Instruction code is divided into two parts namely
operation code and address of data.
Operation code
consisting group of bits to define an operation such as add, subtract, multiply etc.
specify the type of operation to be performed.
Another field is the address field which is used to specify the operand address on which the operation is to be done.

15. Instruction Code In an instruction format:
First 12 bits (0-11) specify an address.
Next 3 bits specify operation code (opcode), or type of operation.
Left most bit specify the addressing mode I
I = 0 for direct address
I = 1 for indirect address

16. Stored Program Organization

17. Computer Registers

18. Addressing Modes
The process of defining the address field of instruction is called addressing modes.
In direct address, the address field in the instruction gives the address of the operand.
In case of the indirect address, the address in the address field gives an address of the memory word in which address operand is found.
Direct and indirect address are separated by bit I. I is 1 for indirect and o for direct.

19. Addressing Modes

20. Effective Address It is the address of the actual operand.
In direct address, content of the address field gives the effective address which is 457 in the given example.
In indirect address, the word in the memory address specified in the address field gives the effective address which is 1350 in the given example.

21. Computer Register

22. Common Bus System
A wire or a collection of wires that carry some multi-bit information is known as bus. Main purpose of bus is to transfer information form one system to another.
It is also known as communication path way which connects all the internal components of the computer to the CPU, main memory and I/O devices.

23. Common Bus System Three functional groups of communication lines: A
Common Bus System Three functional groups of communication lines: A. Data lines (data bus) - move data between system modules. Width is a key factor in determining overall system performance. B Address lines - designate source or destination of data on the data bus. Width determines the maximum possible memory capacity of the system. C. Control lines - control access to and use of the data and address lines.

24. Common Bus System
The basic computer has eight register, memory unit and control unit.
Path must be provided to transfer information from one register to another and from memory to the register.
The number of wires will be excessive if the connection is made between the output of each register and input of other.
A more efficient scheme in transferring information in a system having many register is to use a common bus.

26. Common Bus System
The outputs of seven registers and memory are connected to the common bus.
The specific output that is selected for the bus lines at any given time is determined from the binary value of the selection variables S2,S1 and S0.
The numbers along each output shows the decimal equivalent of the required binary selection.
The lines from the common bus are connected to the inputs of each register and data input of the memory.

27. Common Bus System
The particular register whose LD(load) input is enabled receives the data from the bus during the next clock transition.
The memory receives the content of the bus when its write input is activated.

28. Types of Instructions
On the basis of opcode and addressing mode, the basic computer has three 16-bit instruction code formats:
1. Memory Reference Instructions.
2. Register Reference Instructions.
3. Input/Output Instructions.

29. Basic Instruction Format

30. Memory Reference Instructions
First 12 bits (0-11) specify an address.
3 bits of opcode are used to specify the types of instruction.
Value of opcode ranges from 000 to 110.
If I=0, it is direct addressing mode and if I=1, it is indirect addressing mode.

31. Memory Reference Instructions
Hexadecimal code
Symbol
I = 0
I = 1
Description
AND
0xxx
8xxx
AND memory word to AC
ADD
1xxx
9xxx
ADD memory word to AC
LDA
2xxx
Axxx
LOAD Memory word to AC
STA
3xxx
Bxxx
Store content of AC in memory
BUN
4xxx
Cxxx
Branch unconditionally
BSA
5xxx
Dxxx
Branch and save return address
ISZ
6xxx
Exxx
Increment and Skip if zero

32. Register Reference Instructions
First 12 bits (0-11) specify the register operation.
The next three bits equals to 111 specify opcode.
The last mode bit of the instruction is 0 for register reference instruction.
Therefore, left most 4 bits are always 0111 which is equal to hexadecimal 7.

33. Register Reference Instructions
Symbol
Hexadecimal code
Description
CLA
7800
Clear AC
CLE
7400
Clear E
CMA
7200
Complement AC
CME
7100
Complement E
CIR
7080
Circulate right AC and E
CIL
7040
Circulate left AC and E
INC
7020
Increment AC
SPA
7010
Skip next instruction if AC positive
SNA
7008
Skip next instruction is AC is negative
SZA
7004
Skip next instruction is AC is 0
SZE
7002
Skip next instruction is E is 0
HLT
7001
Halt computer

34. Input / Output Instruction
First 12 bits (0-11) specify the I/O operation.
The next three bits equals to 111 specify opcode.
The last mode bit of the instruction is 1.
Therefore, left most 4 bits are always 1111 which is equal to hexadecimal F.

35. Input/Output Instructions
Symbol
Hexadecimal code
Description
INP
F800
Input character to AC
OUT
F400
Output character from AC
SKI
F200
Skip on input flag
SKO
F100
Skip on Output flag
ION
F080
Interrupt on
IOF
F040
Interrupt off

36. Basic Instruction Format
Hex code of i/o instruction starts with F.
Hex code of register reference instruction starts with the 7.
Hex code of direct memory reference instruction starts with 0-6.
Hex code of indirect memory reference instruction starts with 8-E.

37. Instruction Set Completeness
The set of instruction are said to complete if the computer includes sufficient number of instruction in each of the following categories.
Arithmetic, logical and shift instruction.
Instruction for moving information to and from memory and processor registers.
Program control instructions together with instruction that check the status conditions.
Input and output instructions.

38. INSTRUCTION SET COMPLETENESS
A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function that is known to be computable.
Instruction Types :-
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

39. Timing and Control
The timing for all registers in the basic computer is controlled by the master clock generator.
The clock pulsed are applied to all the flip flops and registers in the system.
The clock pulses do not change the state of register unless enabled by control signals.
These signals are generated in the control unit.
There are two major types of control organization: hardwired control and micro programmed control.

40. Timing and Control
In hardwired control, the control logic is implemented with gates, flip flops, decoders and other digital circuits.
In micro programmed organization, the control information is stored in a control memory. The control memory is programmed to initiate the required sequence of micro operation.

41. Control Unit
CPU is divided into Arithmetic Logic Unit (ALU) and Control Unit (CU).
The function of control unit is to generate relevant timing and control signals to all operations in the computer.
It controls the flow of data between the processor and memory and peripherals.
The control unit directs the entire computer system to carry out stored program instructions.
The control unit co-ordinates the activities of the other two units(ALU and main memory) as well as all peripherals and auxiliary storage devices linked to the linked to the computer.

42. Design of Control Unit
Control units are implemented using one of the two organizations:
i. Hardwired Control Unit: In this, the control logic is implemented with gates, flip flops, decoders and other digital circuits.
ii. Micro-programmed Control Unit: A control memory on the processor contains micro programs that activate the necessary control signals.

43. HARDWIRED CONTROL UNIT
It is implemented as logic circuits (gates, flip-flops, decoders etc.) in the hardware.
This organization is very complicated if we have a large control unit.
In this organization, if the design has to be modified or changed, requires changes in the wiring among the various components. Thus the modification of all the combinational circuits may be very difficult.

44. HARDWIRED CONTROL UNIT
ADVANTAGES
Hardwired Control Unit is fast because control signals are generated by combinational circuits.
(The delay in generation of control signals depends upon the number of gates. )

45. HARDWIRED CONTROL UNIT
DISADVANTAGES
More is the control signals required by CPU; more complex will be the design of control unit.
Modifications in control signal are very difficult. That means it requires rearranging of wires in the hardware circuit.
It is difficult to correct mistake in original design or adding new feature in existing design of control unit.

46. ARCHITECTURE OF HARDWIRED CONTROL UNIT
Opcode
Address

47. Hardwired Control Unit
Control unit consist of:
Instruction Register
Number of Control Logic Gates,
Two Decoders
4-bit Sequence Counter
An instruction read from memory is placed in the instruction register (IR).
The instruction register is divided into three parts: the I bit, operation code, and address part.
First 12-bits (0-11) to specify an address, next 3-bits specify the operation code (opcode) field of the instruction and last left most bit specify the addressing mode I.
I = 0 for direct address
I = 1 for indirect address

48. Hardwired Control Unit
First 12-bits (0-11) are applied to the control logic gates.
The operation code bits (12 – 14) are decoded with a 3 x 8 decoder.
The eight outputs ( D0 through D7) from a decoder goes to the control logic gates to perform specific operation.
Last bit 15 is transferred to a I flip-flop designated by symbol I.
The 4-bit sequence counter SC can count in binary from 0
through 15.
The counter output is decoded into 16 timing pulses T0 through T15.
The sequence counter can be incremented by INR input or clear by CLR input synchronously.

49. Hardwired Control Unit
Opcode of the instruction derives one of the output of opcode decoder high.
At first SC is cleared to zero. As the first clock pulse hits the output of counter and hence counter decoder change and produce sequence of timing signals T0,T1,T2 and so on.
The output of counter decoder and decoded opcode of the instruction causes the control logic to generate a particular control word for the operation.
At the end of each instruction, counter is cleared.
For the next instruction, the opcode produces different output on the opcode decoder and the control will be different and the control unit will perform the different tasks

50. HARDWIRED CONTROL UNIT
For example:
Consider the case where SC is incremented to provide timing signals T0, T1, T 2 , T3, and T4 in sequence. At time T4 , SC is cleared to 0 if decoder output D3 is active. This is expressed symbolically by the statement:
D3 T4 : SC ← 0
The timing diagram shows the time relationship of the control signals.

51. TIMING DIAGRAM

52. MICRO-PROGRAMMED CONTROL UNIT
A micro-programmed control unit is implemented using programming approach. A sequence of micro-operations are carried out by executing a program consisting of micro-instructions.
Micro-program, consisting of micro-instructions is stored in the control memory of the control unit.
Execution of a micro-instruction is responsible for generation of a set of control signals.

53. MICRO-PROGRAMMED CONTROL UNIT
A micro-instruction consists of:
One or more micro-operations to be executed.
Address of next microinstruction to be executed.
Micro-Operations: The operations performed on the data stored inside the registers are called micro-operations.
Micro-Programs: Microprogramming is the concept for generating control signals using programs. These programs are called micro-programs.

54. MICRO-PROGRAMMED CONTROL UNIT
Micro-Instructions: The instructions that make micro-program are called micro-instructions.
Micro-Code: Micro-program is a group of micro-instructions. The micro-program can also be termed as micro-code.
Control Memory: Micro-programs are stored in the read only memory (ROM). That memory is called control memory.

55. MICRO-PROGRAMMED CONTROL UNIT
ADVANTAGES
The design of micro-program control unit is less complex because micro-programs are implemented using software routines.
The micro-programmed control unit is more flexible because design modifications, correction and enhancement is easily possible.
The new or modified instruction set of CPU can be easily implemented by simply rewriting or modifying the contents of control memory.
The fault can be easily diagnosed in the micro-program control unit using diagnostics tools by maintaining the contents of flags, registers and counters.

56. MICRO-PROGRAMMED CONTROL UNIT
DISADVANTAGES
The micro-program control unit is slower than hardwired control unit. That means to execute an instruction in micro-program control unit requires more time.
The micro-program control unit is expensive than hardwired control unit in case of limited hardware resources.
The design duration of micro-program control unit is more than hardwired control unit for smaller CPU.

57. ARCHITECTURE OF MICRO-PROGRAMMED CONTROL UNIT

58. ARCHITECTURE OF MICRO-PROGRAMMED CONTROL UNIT
The address of micro-instruction that is to be executed is stored in the control address register (CAR).
Micro-instruction corresponding to the address stored in CAR is fetched from control memory and is stored in the control data register (CDR).
This micro-instruction contains control word to execute one or more micro-operations.
After the execution of all micro-operations of micro-instruction, the address of next micro-instruction is located.

59. COMPARISON BETWEEN HARDWIRED AND MICRO-PROGRAMMED CONTROL UNIT
Attributes
Hardwired Control
Micro-programmed Control
Speed
Fast
Slow
Cost of Implementation
More
Cheaper
Flexibility
Not flexible, difficult to modify for new instruction
Flexible, new instructions can easily be added
Ability to Handle Complex Instructions
Difficult
Easier
Decoding
Complex
Easy
Applications
RISC Microprocessor
CISC Microprocessor
Instruction Set Size
Small
Large
Control Memory
Absent
Present
Chip Area Required
Less

60. Instruction Cycle a. Fetch and instruction from memory.
Processing required for a single instruction is called an instruction cycle.
The program executed in the computer by going through a cycle for each instruction.
The process of fetching, decoding and executing the instruction is called instruction cycle.
Basic instruction cycle consists of the following phases:
a. Fetch and instruction from memory.
b. Decode the instruction.
c. Read the effective address from the memory, if the instruction has an indirect address.
d. Execute the instruction.

61. Instruction Cycle
The instruction cycle can be broken down into two major phases:
Fetch - CPU reads an instruction from a location in memory
Program counter (PC) register keeps track of which instruction executes next.
Normally, CPU increments PC after each fetch.
Fetched instruction is loaded into the instruction register (IR).
Execute - CPU executes the instruction
The instruction is held in IR is decoded.
Then, the instruction is executed.
May utilize previously changed state of CPU and indirectly other devices.

62. Instruction Cycle

63. Instruction Cycle Fetch and Decode
SC is cleared to 0. It is incremented by one so that timing signal goes through T0,T1 and so on.
PC is loaded with the address of the first instruction.
Micro operation are listed below:

64. Instruction Cycle Determine the type of instruction
Decoder output D7 equals to 1 if instruction is register reference or input/output reference.(opcode 111)
Decoder output D7 equals to o if the instruction is memory reference.(opcode )
Control then inspects the first bit. If D7=0 & I=1 it is memory reference with indirect address. If D7=0 and I=0 it is memory reference with direct address.
If D7=1 and I=0 it is register reference instruction.
If D7=1 and I=1 it is input/output reference instruction.

65. Instruction Cycle Execute the Instruction
Three instruction types are divided into four paths.
The operation related to timing signal T3 are :

66. Input Output Configuration
A computer serves no useful purpose unless it communicates with the external environment.
Instruction and data stored in memory must come from some input device.
Computational results must be transmitted to the user through some output device

67. Input Output Configuration

68. Input Output Configuration
Input Register(INPR) consist of eight bits and hold alphanumeric input information.
The one bit input flag(FGI) is control flip flop. It is 1 when information is available in INPR and cleared to 0 when information is accepted by computer.
The output register(OUTR) works in similar manner.
When computer found FGO is 1, the information from AC is transferred to OUTR and FGO is cleared to 0.
The output device receives the information and set FGO to 1.

69. Program Interrupt
The speed of the peripheral devices are very slow in comparison to that of the computer.
So during i/o operation computer will waste time while checking the flag instead of doing some useful tasks.
One solution for this problem is that computer won’t check the flag continuously but get interrupted whenever the flag is set.
Computer than deviates from what it was doing and take care of the i/o operation.

70. Interrupt Cycle
The interrupt handled by the program can be explained with the help of flow chart.
When R=0, computer goes through an instruction cycle.
During execute phase IEN is checked if it is 1, control checks for flags if both are zero next instruction is executed. If either flag is 1 when IEN is 1, R is set to 1 and it goes through the interrupt cycle.

71. Interrupt Cycle
In interrupt cycle address in PC is stored in some location so that it can be found later.
Here we choose memory location at address 0 to store the return address.

72. Interrupt Cycle

73. Interrupt Cycle

74. Interrupt Cycle
The interrupt cycle is a HW implementation of a branch and save return address operation.
At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1.
At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine.
The instruction that returns the control to the original program is "indirect BUN 0“.

75. "When you realize how perfect everything is you will tilt your head back and laugh at the sky.”
- Buddha