1. buses, crossing switch, multistage network.
University of Technology
Computer engineering and information technology Department
Distributed system :
Forms parallelism.
Classification architecture :
Flynn Taxonomy: SISD,SIMD,MISD and MIMD.
According connection memory - processor :
Share memory:
-according access UMA,NUMA,COMA.
-according connection:
buses, crossing switch, multistage network.
Message system:
-according network topology.
Hybrid system (combination access).
Distributed share memory.

2. Form Parallelism 1 Processors:
University of Technology
Computer engineering and information technology Department
Form Parallelism 1
Processors:
-sequence :execute always only one instruction.
-”look ahead”: looking also to next instruction.
Overlapping phase read and decode with executing instruction.
Function parallelism:
Multi function units.
Chining-”pipeline”.

3. - Multiple Instruction Multiple Data “MIMD” :
University of Technology
Computer engineering and information technology Department
Form Parallelism 2
Chining (Next parts function units).
Implicit processing vector operand.
Explicit vector operand.
Register –register.
- Single Instruction Multiple Data “SIMD” :
ex: processor array, Very Long Instruction Word ”VLIW”.
Memory – memory.
- Multiple Instruction Multiple Data “MIMD” :
ex: Multiprocessor, Multicomputer.

4. Flynn Taxonomy Michael J. Flynn (1966).
University of Technology
Computer engineering and information technology Department
Flynn Taxonomy
Michael J. Flynn (1966).
How much instruction in given moment running and over how much data elements.
Instruction Stream
Single
Multiple
Data
Stream
SISD
MISD
SIMD
MIMD

5. SISD One control unit ,one flow control.
University of Technology
Computer engineering and information technology Department
SISD
One control unit ,one flow control.
From memory read/write always only one value data.
Classical von Neumann architecture.
Input unit
processor
control
Memory
output unit

6. Today architecture of SISD
University of Technology
Computer engineering and information technology Department
Today architecture of SISD
CPU
North bridge
(memory controller)
AGP
RAM
System clock
PCI
south bridge
(I/O controller)
I/O

7. University of Technology
Computer engineering and information technology Department
SIMD
Single control unit (single instruction cache) control multi equal (synchronize) executed units.
Equal operation will execute with various data.
Vector processors: operate over vector execute in single instruction cycle.
(increment over component scalar multiply ).
Work with special HW “ VLIW, EPIC”.
Note: VLIW (Very Long Instruction Word).
EPIC( Explicitly Parallel Instruction Computing).

8. Characteristic : Count execution units (EU). Count scalar instruction.
University of Technology
Computer engineering and information technology Department
Characteristic :
Count execution units (EU).
Count scalar instruction.
Semaphore.
Count bridge scheme.
Count vector instruction.

9. MISD Multiple Various operation over equal data :
University of Technology
Computer engineering and information technology Department
MISD
Multiple Various operation over equal data :
-Data pass at once to all execution units (different parts single data flow ).
-Data pass to first execution unit and his output is input to next …”Micro- pipeline”.
Ex: Carnegie-Mellon, Multi mini processor ”C.mmp” (16p,SIMD,MISD,MIMD)
“Data flow” architecture, systolic array.
Only for integrity, Practically unused.

10. University of Technology
Computer engineering and information technology Department
MIMD
Multi flow “control and data” _ each processor can execute different program on itself data.
Can work asynchronous (on different from MISD).
Processors synchronous for access to share (resources) data.
Computer with multi processor (SM-MIMD).
Multi computer connected in network (DM-MIMD).

11. How can seem MIMD/SIMD? Multiprocessors:
University of Technology
Computer engineering and information technology Department
How can seem MIMD/SIMD?
Multiprocessors:
-Narrow band- communicate through share memory.
-Single (share) address space.
- Assigned data getting by searching program on
share memory locations.
-Semaphore, mutex, barrier.
Multicomputer:
-Free band-communication message system.
-Each process have self memory and address space.
-Located assigned data by effected step (instruction)in program.