1. WP1 - Pixel detectors for HEP tracking and Imaging
Richard Plackett (SR) and Timo Tick (ESR)
ACEOLE 12 Month Meeting, 1st October 09

2. Richard Plackett – 1st 6 months
6 week secondment to PANalytical
Formal internal training on XRD/XRF
On the job training with Pan experts implementing new techniques based on Medipix2 chip
Automatic Known Good Die (KGD) testing and classification – MATLAB based wafer probing system
Prerequisite to large area tiling
Formal training course on MATLAB
On the job training on chip behaviour and classification by local experts
A significant number of wafers sucessfully tested
Reports in Collaboration meetings

3. Automatic Wafer Characterisation
A KS PA200 probestation was automated to allow the automatic testing of readout chips at the wafer level
A custom optical feedback system allows automatic alignment and chip finding to test wafers and individual assemblies
Karl Suss PA200 Probestation
Microscope video feed
Target image
Correlation
Reconstructed chip positions on a Medipix1
Peak finding
Position reconstruction

4. Richard Plackett – LHCb activities
Timepix / Pixel VELO Testbeam Activity
Testbeam Results
Plans for Future Timepix Telescope
RICH Photon Detector Upgrade Proposal
Medipix3 radiation sensitivity measurements
Slides from presentations to VERTEX09 and LHCb RICH upgrade meetings.

5. Recent Testbeam Activity
A Timepix like chip is a candidate for a Pixel VELO upgrade
Required to demonstrate suitability for tracking
Measure efficiency and resolution
Provide information for VELOPIX design
3 testbeams at CERN SPS with 120GeV Pions
June: as Medipix Group to test Telescope concept
July: Running parasitically from CMS SiBit telescope
August: Running parasitically from EUDET/LCFI testbeam
Significant improvements to telescope design at each testbeam

6. Testbeam Telescope V1 and V2
The first testbeam in June proved we could do tracking with Medipix2 chips and the synchronisation scheme worked
The July testbeam took two weeks of data across all areas of interest.
This experience allows us to significantly improve the design of the Timepix Telescope

7. Timepix Telescope 4 Timepix, 2 Medipix planes in telescope
Symmetric positioning of planes around Timepix DUT
Telescope planes mounted at nine degrees in x and y
DUT position and angle controlled remotely by stepper motors
Measurements of resolution with angle, threshold, sensor bias, 3D sensor and timewalk

8. Angled Planes to Boost Resolution
Hits that only affect one pixel have limited resolution (30um pixel region)
Angling the sensor means all tracks charge share and use the ToT information
55um
300um
10o
Timepix (ToT) tracked position vs cluster reconstructed position

9. Results – Resolution Vs Track Angle
Rotation about Y axis
2.5um Estimated track contribution to residual
PRELIMINARY: UNCALIBRATED DATA!!
The tracking uncertainty of the telescope is very competitive, with uncalibrated, uncut data, 2.5um is comparable to EUDET running with 30um pixels (Timepix is 55um)

10. Results – 3D Sensors Efficiency Glasgow double sided CNM sensor
Perpendicular particles passing through a doped hole will deposit less charge in the silicon
The sub-pixel resolution of the telescope allows us to see the efficiency losses due to the anode and cathode holes in the silicon.

11. Design Lessons for VELOPIX
Analogue IS better than Binary, even with 55um pixels, even with clusters and charge sharing
Clustering WILL significantly increase hit multiplicity
Interactions within the sensor will occur often and need to be handled to avoid overflowing the chips for that event
From this data we will determine how many bits ToT we need and optimise on chip the data transport
Timepix (ToT) 5um
Medipix (binary) 11um

12. Plans for a future Timepix Telescope
We plan to add fast readout systems and software synchronisation
High resolution (<3um) as current telescope
Track timing down to 10ns
Link to PMT/external device for trigger and integration of DUTs
Maximum track rate increased up to ~200kHz
Convenient, flexible device as current telescope
Should become baseline LHCb telescope for upgrade work
DUT
New Readout
New Readout
Timing unit

13. LHCb RICH System LHCb RICH must also upgrade to 40Hz electronics
Requires at least HPD photon detector planes to be replaced
Possible to use VELOPIX as base for new MCP photon detector
The Medipix group already has collaborators with experience in this area
Requires high density through Silicon Via technology
Photon
Quartz window and photocathode as HPD and MAPMT
Photoelectron
200V/mm drift field
MCP cascade amplification (~1kV)
Electron shower
Bare readout chip array (no bump bonds)
A Proximity focused MCP tube could perform as well as an HPD with many additional advantages…
40MHz digital readout
Magnetic field tolerance
Low vacuum volume
Higher resolution
Avoids 20kV supply simplifying services

14. 400Mrad Irradiation 60 MRad 460 MRad 400 MRad
Used a calibrated X-ray machine (Seifert RP149)
Beam profile is smaller than the Medipix3 → Two runs:
On the Pixel Matrix 60Mrad
Threshold Variation
Gain Variation
Noise Increase
60 MRad
On the Periphery 400Mrad
Check DACs
E-fuses
Logic functionality
460 MRad
400 MRad

15. Performance after 460MRad
Threshold
Noise
Yield artifact
σ=1.72 ke-
µ=9.3 ke-
σ=12.9 e-
µ=71.6 e-
Threshold can be re-tuned using 5 bit equalisation

16. Performance after 460MRad
Row[0:255]
Yield artifact
Qin=2ke-
After 460MRad there is essentially no gain variation observed

17. Richard Plackett - Conclusions
First months devoted to learning materials analysis techniques, MATLAB and Medipix2/Timepix chip operation
Automatic wafer probe test system developed and successfully operated
A series of test beams were carried out using a large number of Timepix assemblies
Excellent test beam results led LHCb VELO to adopt that approach for the upgrade
Along the way we developed a very accurate and convenient particle telescope we would like to take further, currently being used in SPS crystal collimator studied
New ideas for a large area tiled photon detector were developed
There is the possibility of the VELO chip being used in MCPs or HPDs in the RICH upgrade.
Measurements on the behaviour of the Medipix3 chip 0.13um indicate its suitability for sLHC and other high dose applications (such as x-ray materials analysis and CT)

18. Timo Tick - Outline Low-cost bumping and flip chip solutions
Through Silicon Via (TSV) process development
Large area tiling
GOAL:
TSVs
Read out chip
Work carried out together with Sami Vaehaenen in the framework of WP6 of PH detector R and D

19. Low-cost bump bonding - motivation
Bump bonding (BB) costs for a single detector unit have been over € 200
Readout chip (ROC) : sensor chip (SC) : bump bonding (cost ratio) = 1:2:7!
Imagine building a square meter sized area from detectors with unit area of 1.5 cm2 with 200 € BB unit costs  667 detectors required for and the total BB cost is 1.3 M€!
More pixel detectors are desired to be used in SLCH and the total area will cover tens of square meters - the cost issues is evident
Reliable and cheap bumping technologies do not exist yet for ultra-fine-pitch (UFP) applications, such as Alice/Atlas/CMS/Medipix chips
Here’s a cost estimation how the costs should be shared between readout chip (ROC) bumping, sensor chip (SC) bumping and FC bonding
In the calculated graph, sensor bumping costs are dominating, but in reality flip chip bonding services have become more expensive

20. Low cost bump deposition solutions
Way to realize the goal is to benchmark the manufacturing technologies used in commercial electronics and adapt them for pixel wafers.
Study the technologies and find the essential limits (minimum bump size and pitch) for a low-cost technology to be realized.
To provide cost savings processes have to become faster and the use of expensive and non-flexible process equipment should be avoided or minimized.
Reliable and cheap bumping technologies do not exist yet for ultra-fine-pitch (UFP) applications, such as Alice/Atlas/CMS/Medipix chips.
Focus is directed at applying electroless deposition process (Ni/Pd/Au) under bump metallization (UBM), which is a low-cost solution and enables various solder transfer and flip chip bonding technologies.
Solder transfer tools combined with electroless UBM’s has a very high potential to be the ultimate low-cost bumping solution.
Electroless Ni/Au UBM deposition was demonstrated with 55 µm pitch.

21. Flip chip development work
Flip chip bonding can be done using with or without solder bumps. Anisotropically conductive adhesives (ACF) enable assembly without solder.
The flip chip work can be divided to two main categories:
Optimization of tooling and tuning of software parameters for existing FC bonders (FC150’s).
Search for new bonding equipment which could boost up the throughput, but could still fulfil the resolution criteria.
± 5 µm accuracy should be good enough for pixel detector assembly.
Nickel and carbon nanofibers in polymer matrix will be tested. The films with aligned fibres are the best candidates for achieving ultra-fine pitch with area array pixels.
Chip-to-wafer bonding process is desired to be developed, because it increases the cost efficiency of flip chip assembly.
A report on low cost bumping solutions (D11) is almost ready for publication (due month 10)
ACF’s are interesting because no solder is needed.

22. TSV development
Joint development project started with VTT , duration 12 months
Step 1: (3 months)
Study and evaluation of the available techniques at VTT for the TSV process
Selection of candidate processes
Definition process parameters for individual process steps/equipment
Step 2: (6 months)
Optimize process and manufacture prototype vias on dummy wafers
Preparation the 2 medipix2/3 wafers for processing
Step 3: (3 months)
Manufacture TSV’s on real medipix2/3 wafers
Time (month)
Deliverable
Partner
Layout of test vehicle
CERN 1
Masks for test vehicle
VTT 3
Detailed TSV process description 8
Supply of 2 Medipix2/3 wafers 9
TSV Assemblies based on test vehicle 10
Test report on test vehicle assemblies 11
Delivery of Medipix2/3 assemblies 12
Test report on Medipix2/3 assemblies
Done

23. Test vehicle
Test vehicle was designed to serve the flip chip and the through silicon via (TSV) development work.
Test vehicle has daisy chain and Kelvin test structures to characterize the interconnection yields and resistances at three interfaces:
Flip chip bumps (20852/chip)
TSV’s (196/chip)
BGA joints (100/chip)
Test chips can be used for gathering reliability data during accelerated thermal stress testing.
Layout has been designed to be used also in wafer-level assembly tests
Chip-to-wafer-bonding
Wafer-to-wafer bonding
24 silicon wafers were processed at VTT to evaluate electroless UBM deposition, low-cost flip chip techniques and BGA connections
Probe card for test vehicle has been designed and acquired - ready for measurements

24. TSV development
Detailed process description has been agreed with VTT and CERN
Development of process is started with 6” dummy wafers although CERN wafer are 8”
Test vehicle layout is used to process test chips for yield and quality evaluation
Via etching test are currently being made at VTT
Plan is to move to 8” processing as soon as possible – process description has been done by Sami and Timo
Formal training on TSV at ECTC, san Diego
Informal on the job training at CERN with S. Vaehaenen and during 2 visits (3 weeks in total) with experts at VTT

25. Large area tiling
Study of large area tiling possibilities of detectors (with TSV’s) has been made: Report by the end of Nov. (D month deliverable)
Two concepts exist:
Research focused on BGA mounted detector modules
Work is done in parallel with TSV development develop solutions to BGA mount detectors with TSV’s as soon as they arrive
Carrier board selection and evaluation
BGA bump type selection and evaluation
Set up BGA bumping and assembly procedures
GOAL: to be ready to design the backside layout of the detector chip and to BGA mount the detectors as soon as chips with TSVs come out

26. Carrier board and BGA bump selection
Carrier board requirements for area array solder mounting large silicon chips
Low CTE, high density signal wiring (multilayer wiring), high current wiring for powering and good heat conductivity
Selected candidates: Multilayer ceramics (LTCC), Carbon composite laminates (CCL) and silicon
3 different BGA bump types were chosen for evaluation:
Non collapsible plastic core BGA
Light weight solution, radiation hardness to be proved
Collapsible BGA
Standard technique, reference
Land Grid Array (no bump)
Simplest and cheapest solution, reliability needs to be proved
Silicon
LTCC
CCL
FR-4
CTE [ppm/K]
2.6 6
2-10 16
Thermal Conductivity [W/mK] 13
2-3
~100 (bulk 600)
0.25
Density [g/cm2]
2.3 3
1.9
Young’s modulus [GPa]
130
350
> 100 15
PCBGA
BGA
LGA

27. Carrier board and bump type evaluation
LTCC – Test board has been designed
To evaluate the reliability of the three chosen bump types with temperature cycling tests
Test the radiation hardness of the plastic core balls
Set up a prototype bumping and assembly procedure in CERN SMD lab.
Status: waiting for UBM deposition on dummy chips
CCL – Suppliers have been contacted to acquire reliability data
Mechanical properties received from the supplier need to be verified
Board reliability and radiation tests need to be done
If these preliminary tests are passed, BGA joint evaluation can be done
Status: Negotiating with material supplier
Silicon – Collaboration with Gigatracker project
BGA reliability is not the issue with silicon carriers
Cooling and high current wiring is and solutions to these issues are being investigated in gigatracker project
Gigatracker is not using TSVs but same solutions apply
Timo investigated the processing possibilities at VTT and presented them to Gigatracker cooling group
Status: Agreement to collaborate, Gigatracker group contacting VTT

28. Conclusions - Timo Tick
First months devoted to understanding needs in HEP and other applications
Low cost bumping approaches studied together with S.Vaehaenen
TSV project established with VTT
Large area tiling based on BGA – candidate solutions identified
Test vehicle designed with S. Vaehaenen for low cost bumping, TSV and BGA evaluation
Test vehicle wafers processed at VTT by Timo and Sami
Formal training undertaken at ECTC conference
PhD thesis in print – defence 27th November