1. INFN Pavia / University of Bergamo
Analog front-end design and study of radiation effects on noise in 65 nm CMOS
INFN Pavia / University of Bergamo
M. Manghisoni, L. Ratti, V. Re, G. Traversi, F. De Canio, L. Gaioni, E. Riceputi

2. INFN Pavia activities in the first year of AIDA-2020
Design and test of analog front-end circuits and IP blocks in 65 nm CMOS pixel readout chips:
INFN CHIPIX65 small-scale prototype
RD53A large scale prototype
Study of the noise behavior of 65 nm CMOS transistors at extremely total ionizing dose

3. Pixel analog front-end circuits in 65 nm CMOS
We have designed and submitted two different analog front-end channel for the readout of HL-LHC pixel detectors
Asynchronous (continuous-time) version with ToT information
Synchronous version with zero dead time and Flash ADC

4. Asynchronous analog front-end channel

6. ToT, charge sensitivity and compensation of sensor leakage current

7. Irradiation tests
Increase in the ENC vs CD slope compatible with an increase in the series noise contribution (likely in 1/f noise)

10. 65 nm CMOS synchronous analog processor with zero dead time and Flash ADC (Fermilab/INFN PV)
Charge sensitive amplifier based on regulated cascode gain stage and featuring leakage current compensation
Compact, single ended threshold discriminator featuring auto-zeroing, operated with 40 MHz clock. This implementation is ideally insensitive to device threshold voltage mismatch  trimming DAC not required
2-bit Flash ADC exploited for digital conversion immediately after the preamplifier
Power consumption = 5 µW @ 1.2 VDD (8 µW with 2-bit ADC)

11. Charge-sensitive preamplifier
Regulated cascode design
Active feedback transistor Mf:
1/gm resistor for small signals
Constant current source for large signals
M1 provides a DC path for the detector leakage current
Ri + Ci ensures low frequency operation of the leakage compensation circuit

12. Comparator Operated in two different phases:
reset phase  the comparator gets reset and a proper bias is provided to the two stages – S1, S2, S3 closed
active phase  an active comparison takes place by injecting both the input and the threshold signals Vth at the comparator inputs – S1, S2, S3 open
Comparator able to detect two consecutive hits (large signal followed by a signal close to threshold)
Time-walk close to 12 ns for Qin close to threshold, close to 7 ns with an overdrive charge of 400 e-
Critical transistors properly scaled to optimize threshold dispersion  35 erms with NO trimming DAC

13. Detection of hits in two consecutive bunch crossings
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Detection of hits in two consecutive bunch crossings
A prototype chip with a 16x16 matrix was submitted for fabrication as a MiniASIC at the end of May (2-bit Flash ADC with power-down capability)
20 x 31 µm floorplan for the analog section

14. Study of TID effects on noise beyond 100 Mrad
A test chip was submitted and fabricated with the TSMC 65 nm LP CMOS process, including NMOS and PMOS transistors (standard interdigitated layout) with W in the range 0.12 – 600 µm, L in the range 65 – 700 nm
NMOS and PMOS transistors were irradiated with 10-keV X-rays from a 50 kV X-ray machine at INFN Laboratori Nazionali di Legnaro (Italy) and at CERN, with a dose rate of about 2 krad(SiO2)/s
MOSFETs were biased during irradiation in the worst-case condition, that is, with all terminals grounded, except the gate of the NMOS, which was kept at VDD = V
Irradiation and following measurements were performed at room temperature. During the time between irradiation and measurements, the devices were kept at about 0 °C to prevent annealing effects

15. Modeling lateral leakage in NMOSFETs
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Modeling lateral leakage in NMOSFETs
Radiation induced positive charge trapped in STI oxides may turn on lateral parasitic transistors. Initially, with increasing dose a larger and larger portion of the STI sidewall gets inverted.
The effective gate width, oxide thickness and capacitance are determined by the extension of the inverted regions along sidewalls.
At first, only the sidewall bottom is inverted because bulk doping is lower in that region; at increasing TID, the inversion region extends towards the surface, involving thinner STI oxide regions.
At higher doses, negative charge trapped at interface states compensates positive oxide charge, and then may even become dominant
Main transistor
finger
Source
Drain
Gate
Lateral parasitic
devices
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16. NMOSFETs – up to 600 Mrad low current density
Moderate 1/f noise increase, no increase in the white noise region is detected
The behavior as a function of the current density is different at high TID, as compared to 10 Mrad
At 200 Mrad (and even 600 Mrad), at low ID 1/f noise increase with respect to pre-irradiation values is smaller than at 10 Mrad

17. NMOSFETs – up to 600 Mrad low current density
At 200 Mrad (and even 600 Mrad), at low ID 1/f noise increase with respect to pre-irradiation values is smaller than at 10 Mrad
This can be correlated with the evolution of radiation effects at increasing TID and with the behavior of ID vs VGS

18. NMOSFETs – up to 600 Mrad high current density
At higher currents, 1/f noise increases by approximately the same amount as at smaller currents when the device is exposed to 200 Mrad and 600 Mrad TID

19. NMOSFETs – 1/f noise coefficient
The effect of 1/f noise increase can be nonnegligible: at 600 Mrad the 1/f noise coefficient increases by about a factor 3 at low currents
(70% increase of the contribution to the ENC of a detector readout channel)
A possible explanation of this behavior is that at very high doses negative charge trapped in interface states at the STI oxides gradually compensates oxide-trapped positive charge, switching off lateral parasitic transistors
Noise contributions by these parasitic devices become less important; 1/f noise increase from 200 Mrad to 600 Mrad can be explained by other effects (increase of border traps in gate oxides, defects in spacer dielectrics…)

20. NMOSFETs – ID variation
At low TID, positive charge in STI oxides switches on lateral devices, increasing ID (for the same VGS)
At higher doses negative charge trapped in interface states at the STI oxides gradually compensates oxide- trapped positive charge, switching off lateral parasitic transistors and reducing ID (for the same VGS)

21. Threshold shift
This is confirmed by the behavior of the radiation- induced threshold shift, which in NMOSFETs is negative at 10 Mrad and positive at 200 Mrad and 600 Mrad.
Because of the effect of interface states, ID vs VGS curves are also stretched at high TID.

22. PMOSFETs – 1/f noise – low current density
Again no effect is detected in the white noise region, while 1/f noise moderately increases.
Lateral parasitic devices do not play a role here (positive charge is accumulated both in oxides and at interface states), so there is no dependence on the drain current density

23. PMOSFETs – 1/f noise coefficient
The effect of 1/f noise increase can be nonnegligible: at 600 Mrad the 1/f noise coefficient increases by about a factor 2
(40% increase of the contribution to the ENC of a detector readout channel)

24. PMOSFETs – ID variation

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Ionizing radiation effects on the signal-to-noise ratio in a pixel readout channel
The noise data reported here can provide the basis to estimate the performance of an analog front-end for pixel detectors at extremely high TID
Even at a signal peaking time of 25 ns, the impact of the radiation-induced 1/f noise increase can be sizable in the bandwidth of an analog channel
This plot shows the noise voltage spectrum of an NMOS with W/L =20/0.13, before irradiation and at 600 Mrad TID, calculated using data extracted from measurements
The transfer function of an RC2-CR semigaussian shaper with 25 ns peaking time is superimposed to the spectra
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Conclusions
A complete analysis of the noise measurements after irradiation can provide a model for the noise behavior of 65 nm CMOS transistors at extremely high TID
In the second year of AIDA, INFN Pavia will contribute to the design work for the submission of the RD53A prototype, and to the testing of smaller 65 nm CMOS prototypes of pixel front-end chips
INFN Pavia is interested to include a chip in the RD53A engineering run, where peripheral TSVs can be tested
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27. Back-up slides